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TAS2120 Datasheet(PDF) 69 Page - Texas Instruments |
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TAS2120 Datasheet(HTML) 69 Page - Texas Instruments |
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69 / 113 page  This register provides the status of latched interrupts. Table 7-47. INT_LATCH_3 Register Field Descriptions Bit Field Type Reset Description 7 INT_LTCH3[7] R 0h Interrupt due to over temperature detected 0h = No interrupt 1h = Interrupt 6 RESERVED R 0h Reserved 5 RESERVED R 0h Reserved 4 RESERVED R 0h Reserved 3 INT_LTCH3[3] R 0h Interrupt due to Class-D Over current protection 0h = No interrupt 1h = Interrupt 2 INT_LTCH3[2] R 0h Interrupt due to Over voltage on PVDD supply. 0h = No interrupt 1h = Interrupt 1 RESERVED R 0h Reserved 0 RESERVED R 0h Reserved 7.1.47 INT_LATCH_4 Register (Address = 64h) [Reset = 00h] Return to the Summary Table. This register provides the status of latched interrupts. Table 7-48. INT_LATCH_4 Register Field Descriptions Bit Field Type Reset Description 7 INT_LTCH4[7] R 0h Interrupt due to VBAT under voltage detection 0h = No interrupt 1h = Interrupt 6 RESERVED R 0h Reserved 5 RESERVED R 0h Reserved 4 RESERVED R 0h Reserved 3 RESERVED R 0h Reserved 2 INT_LTCH4[2] R 0h Interrupt due to clock halt flag 0h = No interrupt 1h = Interrupt 1 RESERVED R 0h Reserved 0 RESERVED R 0h Reserved 7.1.48 NG_IDLE_STATUS Register (Address = 65h) [Reset = 00h] Return to the Summary Table. This register provides the status of noise gate. Table 7-49. NG_IDLE_STATUS Register Field Descriptions Bit Field Type Reset Description 7 NG_STATUS R 0h Noise mode status bit 0h = Device not in Noise gate mode 1h = Device in Noise gate mode 6 MUSIC_EFF_STATUS R 0h Music efficiency mode status bit 0h = Device not in music efficiency mode 1h = Device in music efficiency mode www.ti.com TAS2120 SLASFC6A – AUGUST 2024 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: TAS2120 |
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