MP3924 datasheet(19/56 Pages) MPS

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MP3924

– QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

MP3924 Rev. 1.0

MonolithicPower.com

7/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

OPERATION

The MP3924 is a quad-output power source

equipment (PSE) power controller for IEEE

802.3af/at

power

over

Ethernet

(PoE)

applications. The device establishes a method

of communication between the powered device

(PD) and PSE with detection, classification, and

marked events. The MP3924 also provides

functions for current and voltage protections in

automatic mode as well as I2C command

control mode.

Power Supply

The MP3924 is designed for PoE applications

that require a 44V to 57V input. The MP3924

powers the output port from this input source,

then generates an internal 3.3V for the digital

and analog circuits. The VCC regulator is

enabled after VIN powers

on. When VIN

exceeds VIN_UVLO, the part is enabled after a

delay (tPOR). All functions can be enabled or

disabled by both VCC and EN going above or

below the under-voltage lockout (UVLO) value,

respectively.

The MP3924 uses the PORT_ENABLE register

to disable functions related to all ports, as well

as functions related to individual ports. The

PORT_ENABLE register does not include VIN,

VCC, or EN UVLO.

The device can be reset by any of the below

conditions:

 VIN or VCC UVLO

 EN turning off

 Writing 0 to the ENAL bit

After the MP3924 resets, all internal register are

set to their default values. The following pins

are read and latched into the internal registers:

 AUTO

 MID

 CLS5

 PMAX

 A3~A0

During normal operation, changes to these pins

do not affect the registers.

The MP3924 includes one VIN over-voltage

protection (OVP) threshold at about 65V. All

ports shut down if input OVP is triggered. The

MP3924

outputs

can

restart

with

new

detection cycle after OVP recovery.

PD Detection

In normal idle operation, the MP3924 detects

the output port for a valid PD connection, which

typically has a 24.9k

Ω resistance (see Figure 3).

80ms

OUTx

VIN

140ms

Detection for 24.9k

Discharge

Classify

VIN (4V)

VIN (8V)

Figure 3: PD Detection Process

During this detection process, the MP3924

generates a two-phase voltage (4V/8V) through

the

OUTx

pin.

Meanwhile,

the

external

MOSFET is off (see Figure 4).

OUTx

VIN

4V/8V

Current

Sense

Figure 4: PD Detection Block Diagram

The OUTx pin sinking current capability is

limited to about 1.2mA. The current and voltage

through the OUTx pin are measured. If the

effective resistance with the two-point test is

valid, this means that one PD device is

connected to the PSE port. The MP3924

integrates a filter to avoid 50Hz/60Hz power line

noise.

After the detection cycle, the DETCx bit is set,

and an interrupt signal is generated to report

that detection has completed. The host can

read

each port’s DET/CLS_RESULT register to

obtain the detection results. After one detection

cycle, the MP3924 enters classification mode if

the PD connection is valid.

If the output port is shorted or the detected

capacitance is too high, the OUTx pin limits the

MP3924 Datasheet(PDF) 19 Page - Monolithic Power Systems

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