MP3924 datasheet(33/56 Pages) MPS

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MP3924

– QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

MP3924 Rev. 1.0

MonolithicPower.com

7/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

D[0]

PEC_M

Masks the interrupt signal for power enable status change interrupt. Set this bit to 0

to disable the interrupt function.

Write 1 to enable the interrupt function; write 0 to disable the interrupt function.

“A” is “1” if the AUTO

pin is set high during start-

up or a reset. “A” is “0” if the AUTO pin is set low.

These bits only disable the response from the INT1 and INT2 pins. The corresponding interrupt bit

always changes. The device cannot mask certain interruptions during start-up or a reset event,

including VIN under-voltage lockout (UVLO) and VCC UVLO.

INTERRUPT PRIORITY (02h)

Read/write

Bits

Bit Name

Default Value

Description

D[7]

VINF_P

Selects if the INT2 pin responds to a VIN power failure interrupt signal.

D[6]

STF_P

Selects if the INT2 pin responds to a start-up failure interrupt signal.

D[5]

OCP_P

Selects if the INT2 pin responds to an over-current (OC) interrupt signal.

D[4]

CLSC_P

Selects if the INT2 pin responds to a classification completion interrupt signal.

D[3]

DETC_P

Selects if the INT2 pin responds to a detection completion interrupt signal.

D[2]

DCDIS_P

Selects if the INT2 pin responds to a DC load disconnect interrupt signal.

D[1]

PGC_P

Selects if the INT2 pin responds to a power good (PG) status change interrupt

signal.

D[0]

PEC_P

Selects if the INT2 pin responds to a power enable status change interrupt signal.

If a bit is set to 1, the INT2 pin pulls low in response to the corresponding interrupt signal. The INT1 pin

responds to all interrupt sources, as long as they are not masked. INT2 only responds to the interrupt

sources that are not masked.

MP3924 Datasheet(PDF) 33 Page - Monolithic Power Systems

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