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MP3924 Datasheet(PDF) 11 Page - Monolithic Power Systems |
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MP3924 Datasheet(HTML) 11 Page - Monolithic Power Systems |
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11 / 56 page ![]() MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 11 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 54V, PGND, DGND, SGND1, and SGND2 are connected together, RSENSE = 0.25Ω, TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Logic Interface (SCL, SDAI, SDAO, INT1, INT2, MID, A0, A1, A2, A3, AUTO, CLS5) Input logic low voltage VLI 0.4 V Input logic high voltage VHI 2 V Logic input current For SCL, SDAI -1 +1 µA Open-drain output logic low voltage VLO Sink current = 3mA, SDAO, INT1, INT2 0.4 V Open-drain output logic high leakage Open drain to 3.3V 1 µA Internal pull-up/down Resistance RUP A0, A1, A2, A3, AUTO, MID to VCC, CLS5 to DGND 50 kΩ Notes: 6) Guaranteed by over-temperature correlation. 7) Guaranteed by engineering sample characterization. 8) If CLS5 is enabled, the MP3924 treats the classification current range from the upper of class 4 to the classification current limit as class 5. 9) Guaranteed by detection time, classification time, and start-up delay time. |
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