MP3924 datasheet(28/56 Pages) MPS

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MP3924

– QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

MP3924 Rev. 1.0

MonolithicPower.com

7/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

the acknowledgement clock pulse. The receiver

must pull down the SDA line during the

acknowledge clock pulse so that it remains low

during the high period of this clock pulse.

Figure 17 shows the data transfer sequence.

After the start condition (S), a slave address is

sent. This address is 7 bits long followed by an

8th data direction bit (R/W). A 0 indicates a

transmission (write), while a 1 indicates a

request for data (read). A data transfer is

always terminated by a stop condition (P)

generated by the master. However, if a master

must communicate on the bus, it can generate

a repeated start condition (Sr) and address

another slave without first generating a stop

condition.

Start

Condition

Stop

Condition

Address

Data

Figure 17: Complete Data Transfer

The MP3924 includes a full I2C slave controller.

The

I2C

slave

fully

complies

with

I2C

specification requirements. It requires a start

condition, a valid I2C address, a register

address byte, and a data byte for a single data

update. The MP3924 acknowledges that it has

received each byte by pulling the SDA line low

during the high period of a single clock pulse. A

valid I2C address selects the MP3924. The

MP3924 performs an update on the falling edge

of the LSB byte.

Figure

shows

I2C

write

example.

Slave Address

Write Data

8 Bits

Master to Slave

Slave to Master

A = Acknowledge (SDA = Low)

S = Start Condition

P = Stop Condition

NA = Not Acknowledge (SDA = High)

Write (Wr) = 0

Read (Rd) = 1

Figure 18: I2C Write Example

Figure 19 shows an I2C write example.

Slave Address

Read Data K

Master to Slave

Slave to Master

A = Acknowledge (SDA = Low)

S = Start Condition

P = Stop Condition

NA = Not Acknowledge (SDA = High)

8 Bits

Slave Address

8 Bits

Write (Wr) = 0

Read (Rd) = 1

Read register data from current register location

Sr = Repeat

Start Condition

Figure 19: I2C Read Example

Figure 20 shows that the 0x00C address has a different read command from the standard I2C.

0x0C

Interrupted Device Address

Master to Slave

Slave to Master

A = Acknowledge (SDA = Low)

S = Start Condition

P = Stop Condition

NA = Not Acknowledge (SDA = High)

8 Bits

Write (Wr) = 0

Read (Rd) = 1

Read device address data by alert response address

Sr = Repeat

Start Condition

Figure 20: 0x0C Read Example

MP3924 Datasheet(PDF) 28 Page - Monolithic Power Systems

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