MP3924 datasheet(41/56 Pages) MPS

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MP3924

– QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

MP3924 Rev. 1.0

MonolithicPower.com

7/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

STATUS REGISTERS

POWER_SOURCE_STATUS1 (20h and 21h)

(20h) Read-only

(21h) Read and clear

Bits

Bit Name

Default Value

Description

D[7]

FETF4

Indicates whether an external power MOSFET failure has occurred. This bit is set

to 1 if the external MOSFET on the corresponding port has failed. If this occurs, the

current limit cannot be reached, or the OUTx pin is high after start-up.

D[6]

FETF3

D[5]

FETF2

D[4]

FETF1

D[3]

VCCUV

Indicates whether a VCC under-voltage condition has occurred. This bit is set to 1

if VCC has recovered from a shutdown or reset condition.

D[2]

OTP

Indicates whether an over-temperature (OT) condition has occurred. This bit is set

to 1 if the junction temperature exceeds 150°C. For more details, see the Over-

Temperature Protection (OTP) section on page 28.

D[1]

VINOV

Indicates whether a VIN over-voltage (OV) condition has occurred. This bit is set to

1 if VIN exceeds 65V.

D[0]

VINUV

Indicates whether a VIN under-voltage (UV) condition has occurred. This bit is set

to 1 if VIN drops below 29.5V.

Read and Clear (0x21h) means that the bit is reset after a read operation. If read on 0x20h, the bits are not

cleared.

POWER_SOURCE_STATUS2 (22h and 23h)

(22h) Read-only

(23h) Read and clear

Bits

Bit Name

Default Value

Description

D[7:2]

RESERVED

Reserved.

D[1]

VINOK

Indicates whether the VIN source power is working normally. This bit is set to 1 if

VIN exceeds 40V.

D[0]

OVPMAX

Indicates whether a power overload condition has occurred. This bit is set to 1 if

the total power load on all ports exceeds the PMAX threshold set by the PMAX pin.

DET/CLS_COMPLETE_STATUS (24h and 25h)

(24h) Read-only

(25h) Read and clear

Bits

Bit Name

Default Value

Description

D[7]

CLSC4

Indicates whether a port has completed its classification process. These bits are

set to 1 if classification has completed on the corresponding bit.

D[6]

CLSC3

D[5]

CLSC2

D[4]

CLSC1

D[3]

DETC4

Indicates whether a port has completed its detection process. These bits are set to

1 if detection has completed on the corresponding bit.

D[2]

DETC3

D[1]

DETC2

D[0]

DETC1

MP3924 Datasheet(PDF) 41 Page - Monolithic Power Systems

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