MP3924 datasheet(25/56 Pages) MPS

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MP3924

– QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

MP3924 Rev. 1.0

MonolithicPower.com

7/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

the PD input voltage is high, a 250ms discharge

timer works with a 100k

Ω load between the

OUTx pin and VIN. If the PD input exceeds

2.4V, a secondary 500ms discharge timer

begins. If the PD input voltage does not fall

below 2.4V after the two discharge times, then

the

MP3924

set

0010

the

LEGACY_DETECT_RESULTx registers.

After legacy detection starts, a fixed current is

charged to the PD input. The voltage difference

between two points is used to calculate the

effective capacitance.

the

capacitance

is too

great

and the

measured voltage difference is below 0.5V,

then

the

MP3924

reports

0110.

the

capacitance is too low and the measured

voltage reaches 18.5V, then the MP3924

reports 0100 or 0101. All of these results are

invalid in legacy detection.

Table 1: Legacy Detection Measurements

Parameter

Value

Units

Minimum measurable

capacitance

µF

Maximum measurable

capacitance

100

µF

Capacitance test charge

current

500

µA

Nominal measurement time

150

Maximum voltage before

start measurement

2.4

Duration of first port

discharge period

250

Duration of second port

discharge period

500

Maximum voltage during

measurement

18.5

If legacy detection is enabled and a legacy

device is detected in automatic mode, then the

detection

status

reported

the

LEGACY_DETECT_RESULTx

registers.

However,

the

device

does

not

start

immediately, as it requires a host command

through the I2C.

If LEGENx is set to 01 or 10 in automatic or

semi-automatic mode, there is initially one

standard

detecting

cycle.

the

standard

resistance detection result is valid, then the

MP3924 does not continue legacy detection

and the classification process begins instead. If

the standard resistance detection result is not

valid and legacy detection is valid, the MP3924

does not start the classification process, even if

the CLSENx bit is set. In this scenario, a

software command is required to trigger the

classification process.

If the following conditions are met, then PON

automatically powers the port (even if the

classification result does not match, or there is

an OC condition):

 PON is enabled by the software after the

legacy detection is determined to be valid.

 The MP3924 is in automatic or semi-

automatic mode.

If the LEGENx bit is enabled in automatic or

semi-automatic mode, the legacy detection

result

repeats

and

refreshes

the

LEGACY_DETECT_RESULTx registers. This

process repeats until the

LEGENx bit

disabled. In manual mode, legacy detection

occurs once, then the LEGENx bits resets

automatically. It is recommended to use manual

mode.

Operation Modes

The MP3924 provides four operation modes to

flexibly control PoE communication and start-up:

automatic mode, semi-automatic mode, manual

mode, and shutdown mode. The AUTO pin and

the MODEx bits set the different modes, which

are described below in greater detail.

Automatic Mode

In automatic mode, the MP3924 automatically

controls

and

responds

all

detection,

classification,

and

start-up

functions.

The

MP3924 handles these processes for each port

independently and without external I2C control.

Float the AUTO pin to force the MP3924 to

work in automatic mode.

In automatic mode, the MODEx bits are set to

11 when device turns on. The AUTO pin status

is only read once when the device turns on or

the MP3924 is reset. If a master is connected to

the MP3924 via the I2C, then the master can

change

the

MODEx

bits

change

the

operation mode. If there is no valid PD on the

port in automatic mode, then the MP3924

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