MP3924 datasheet(32/56 Pages) MPS

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MP3924

– QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

MP3924 Rev. 1.0

MonolithicPower.com

7/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

INTERRUPT REGISTERS

INTERRUPT (00h)

Read-only

Bits

Bit Name

Default Value

Description

D[7]

VINF

Interrupt signal for VIN power failure. If this bit is set to 1, one of the following

scenarios has occurred:



The power on VIN is below 29.5V



VIN over-voltage protection (OVP)



VCC is under the under-voltage lockout (UVLO) threshold



Thermal shutdown



A power MOSFET failure



A PMAX event

D[6]

STF

Interrupt signal for a start-up failure. If this bit is set to 1, at least one of the ports has

experienced a start-up failure, or if a port shuts down due to the start-up inrush

current.

D[5]

OCP

Interrupt signal for over-current (OC) conditions. If this bit is set to 1, at least one of

the ports has met the ILIMT current limit timer or the ICUT OC timeout condition.

D[4]

CLSC

Interrupt signal for classification completion. This bit is set to 1 if at least one port

has completed its classification process.

D[3]

DETC

Interrupt signal for detection completion. This bit is set to 1 if at least one port has

completed its detection process.

D[2]

DCDIS

Interrupt signal for a disconnected DC load. This bit is set to 1 if at least one port

has had its DC load disconnected (load < 7.5mA).

D[1]

PGC

Interrupt signal for power good (PG) status change. This bit is set to 1 if at least one

port has a new PG status.

D[0]

PEC

Interrupt signal for power enable status change. This bit is set to 1 if at least one

port has changed its enable or disable status.

Read the register address with an R/C byte, or write 1 to CLRAIN to reset the corresponding bit. The

IN1 and INT2 pins go low to report if an interrupt bit is set to 1. These pins do not go low if the interrupt

signal is masked.

INTERRUPT_MASK (01h)

Read/write

Bits

Bit Name

Default Value

Description

D[7]

VINF_M

Masks the interrupt signal for VIN power failures. Set this bit to 0 to disable the

interrupt function.

D[6]

STF_M

Masks the interrupt signal for start-up failures. Set this bit to 0 to disable the

interrupt function.

D[5]

OCP_M

Masks the interrupt signal for over-current (OC) conditions. Set this bit to 0 to

disable the interrupt function.

D[4]

CLSC_M

Masks the interrupt signal for classification completion. Set this bit to 0 to disable the

interrupt function.

D[3]

DETC_M

Masks the interrupt signal for detection completion. Set this bit to 0 to disable the

interrupt function.

D[2]

DCDIS_M

Masks the interrupt signal for DC load disconnection. Set this bit to 0 to disable the

interrupt function.

D[1]

PGC_M

Masks the interrupt signal for power good (PG) status change interrupt. Set this bit

to 0 to disable the interrupt function.

MP3924 Datasheet(PDF) 32 Page - Monolithic Power Systems

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