MP3924 datasheet(27/56 Pages) MPS

27 / 56 page

MP3924

– QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

MP3924 Rev. 1.0

MonolithicPower.com

7/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

the lower 4 bits are set by A3~A0 pins. When

the master sends an 8-bit address value, the 7-

bit I2C address should be followed by a 0 or 1 to

indicate a write or read operation, respectively.

The MP3924 works as a slave and supports

standard mode (100kbps)

and fast mode

(400kbps) communication.

The I2C is a two-wire, bidirectional serial

interface consisting of a data line (SDA) and a

clock line (SCL). The lines are externally pulled

to a bus voltage when they are idle. When

connecting

the

line,

master

device

generates the SCL signal and device address,

then arranges the communication sequence. To

support communication with an isolated host

controller, the data interface is split into two

ports:

SDAI

and

SDAO.

For

non-isolated

applications,

SDAI

and

SDAO

can

connected to on another.

The MP3924 includes one alert response

address for MP3924 devices that are connected

through the address 0x0C (000 1100). If the

bus master controller sends the alert response

address when INT1 is low during an interrupt

event, then the MP3924 with the interrupt

request responds with its device address on the

SDAI line before releasing the INT1 line.

If two MP3924 devices respond simultaneously,

then

the

device

with

the

lower

address

succeeds in transmitting to the master via the

SDAI and SDAO lines. The device that attempts

to send a 1 but detects a 0 on the SDAI line

does not respond. After this, the MP3924 with

the higher address finishes responding. Its INT1

pin remains low until it receives the host

controller’s next alert response address read.

The

MP3924 has one global address: 0110000.

This means that the host controller can write to

multiple MP3924 devices through the address

0x60 (01100000). If the host controller reads

multiple MP3924 through the address 0x61

(01100001), it works as an alert response

address.

While reading or writing, the MP3924 register

address is determined by the host command.

After each read/write data byte operation, the

byte, and the host can read/write the next byte

without the new address command information.

If the system works with several host controllers,

the address set by host 1 can respond to host 2,

if host 1 does not have data to read/write in that

address. If different registers must be read or

written, one address information is required to

set the correct register address.

I2C Data Validity

One

clock

pulse

generated

for

each

transferred data bit. The data on the SDA line

must be stable during the high period of the

clock. The high or low state of the data line can

only change when the clock signal on the SCL

line is low (see Figure 15).

Figure 15: Bit Transfer on the I2C Bus

The start (S) and stop (P) commands are

signaled by the master device, which signifies

the beginning and the end of the I2C transfer. A

start command is defined as the SDA signal

transitioning from high to low while the SCL

signal is high. A stop command is defined as

the SDA signal transitioning from low to high

while the SCL signal is high (see Figure 16).

Start Condition

Stop Condition

Figure 16: Start and Stop Conditions

Start and stop commands are always generated

by the master. The bus is considered to be

busy after a start command. The bus is

considered to be free again

a minimum of 4.7μs

after the stop condition. The bus remains busy

if a repeated start (Sr) command is generated

instead of a stop command. The start (S) and

repeated start (Sr) commands are functionally

identical.

I2C Transfer Data

Every byte put on the SDA line must be 8 bits

long. Each byte has to be followed by an

acknowledge (ACK) bit. The acknowledge clock

pulse

generated

the

master.

The

transmitter releases the SDA line (high) during

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