MP3924 datasheet(20/56 Pages) MPS

20 / 56 page

MP3924

– QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

MP3924 Rev. 1.0

MonolithicPower.com

7/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

sink current to about 1.2mA. Then the detection

cycle ends.

If the output port has an open circuit in the first

phase detection period, the MP3924 ends the

detection cycle. If the OUTx pin has a low

impedance

PGND,

detection

ends

immediately.

For other invalid resistance signatures, the

MP3924

ends

detection

after

two-phase

detection. After one invalid detection result, the

MP3924 stays in idle mode and re-enables

detection within an 80ms port reset time. In

midspan mode, there is one delay time (about

2.8s) before the 80ms reset time.

Midspan Mode

If a port is set to midspan mode, the device

waits about 2.8s before attempting to detect a

connection.

This

can

avoid

detection

collision. Midspan mode can be set or reset by

the MID pin before the MP3924 starts up.

Midspan mode can also be configured via the

MIDx bits via the I2C interface during normal

operation. If the detection is valid, the device

exits midspan mode.

PD Classification

If the PD detection resistance is valid, the

device enters classification mode to measure

the power level of the connected PD. Different

classifications support 4W, 7W, 15.4W, or 30W

power

the

port.

Based

the

IEEE802.3af/at standard, the MP3924 provides

one additional class: Class 5 (see Figure 5).

Class 5 classification has a 40W load capability,

which is valid when the CLS5_EN bit is enabled

and the classification current exceeds the Class

4 upper current threshold. If Class 5 is not

enabled, a classification current that exceeds

50.5mA

results

over-current

(OC)

condition and a classification failure. If Class 5

is enabled, a classification current that exceeds

50.5mA results in a Class 5 classification level.

In this scenario, an OC condition refers to when

the current has triggered the current limit

threshold. OC conditions can occur with all

classes.

The CLS5 pin is internally pulled down to

DGND to disable Class 5 classification. Pull the

CLS5 pin high during a power-on reset (POR)

enable

Class

classification.

Another

method to enable Class 5 is to use the enable

the CLS5_ENx bits on a port.

During classification, the MP3924 outputs a

18V voltage on the OUTx pin (see Figure 5).

The device then measures the current though

the OUTx pin to determine the classification

level. After classification is complete, the status

bits

(CLSCx)

and

interrupt

are

set.

The

classification result is stored in the DET/CLS

Result register.

OUTx

VIN

18V

Current

Sense

Figure 5: Classification Block Diagram

Classification is based on the IEEE802.3at

standards. If a classification result is in Class

0~3, the MP3924 only performs one-time

classification in accordance with IEEE 802.3af.

If Class 4 or Class 5 is detected in the first

classification event, the MP3924 performs a

second classification event when the voltages

on VIN and OUTx are the same. 2-event

classification can be enabled by 2EVNTENx

(see Figure 6).

OUTx

VIN

Valid

Detection

Class 1~3

2-Event for Class 4/5

Figure 6: 1-Event and 2-Event Classification

Between the two classifications, the MP3924

performs two time mark events between VIN

and OUTx with an 8.8V mark voltage. The

second classification result must be equal to the

first classification result, or the classification is

considered invalid.

After each 2-event classification, the output port

generates an 8.8V voltage to perform the mark

MP3924 Datasheet(PDF) 20 Page - Monolithic Power Systems

MP3924 Datasheet(HTML) 20 Page - Monolithic Power Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL