MP3924 datasheet(22/56 Pages) MPS

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MP3924

– QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

MP3924 Rev. 1.0

MonolithicPower.com

7/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

controlled by the ICUTx bits), then a timer (tICUT)

is enabled to record the OC condition.

8The

port

turns

once

this

timer

finishes

counting. If the load current exceeds VCUT and

triggers VILIM / RSENSE, then the GATE pin

regulates the load at the current limit level. An

additional timer (tILIM) is enabled to record the

current limit event. tILIM is counted even if the

MP3924 is in current foldback mode.

VCUT detects the OC threshold, which is below

the VILIM threshold. tICUT starts counting when

the OC condition begins. If the load current

drops

below

VCUT,

tICUT

does

not

reset

immediately. Instead, tICUT counts down at a

rate that is 1/16 of how quickly is counts up.

The tICUT timer records for a total of 60ms for

every 0.96s + 0.06s detection window.

If the port shuts down due to an OC condition,

the port can be re-enabled only after tICUT

counts down to 0. This logic can detect a short

or repeated OC condition. The logic also

protects

the

external

MOSFET

from

overheating. tILIM and tNRUSH operate with the

same logic.

The over-current protection (OCP) timer does

not reset even if the device shuts down or the

EN bit turns off. This means that the port cannot

be re-enabled until the timer counts to 0 again.

In manual mode, the host should read the Read

and Clear register address continuously until

the register is reset to 0. Then the port is re-

enabled. In automatic mode, the MP3924

automatically restarts after the timer counts

down to 0.

When tICUT is completed, the related OUT port

shuts down (see Figure 10). At the same time,

the

POWER_STATUS

and

OVER_LOAD_STATUS registers are set to

indicate the power condition.

The default VCUT is different for Classes 0~3

than Class 4 and Class 5. VCUT can also be

configured. VILIM has three fixed values for

Classes 0~3, Class 4, and Class 5.

OUTx

VIN

ILIM

Current

tCUT

ICU T

<60ms

60ms

SR1

SR2

SR1 = 16 x SR2

OCP

>0.96s

Detect.

Figure 10: ICUT Over-Current Detection

The GATE pin typically has a 43µA source

current capability for current limit regulation,

which means that the output voltage maximum

start-up slew rate can be controlled by IGATE /

CGD (CGD is the capacitance between the

external MOSFET’s gate and drain). When the

GATE pin

’s voltage is pulled down to 1V by a

weak discharge current, the voltage is latched

to 0V with a strong pull-down current until the

next start-up event. If the load current ramps up

quickly and triggers the VSCP fast-off voltage

threshold, the MP3924 shuts down port power

quickly to protect the MOSFET. The load at the

current limit level is regulated until the timer

(tILIM) counts down.

The MP3924 shuts down the corresponding

output port if an ICUT or ILIM event occurs, and

the related fault bits are set. The following

registers are also affected:

 The

PGx

and

PENx

bits

the

POWER_STATUS register are cleared.

 The

DET/CLS_RESULTx

and

PORTx_VOLTAGE/CURRENT register are

cleared.

 The PGCx and PECx bits in the

POWER_STATUS_CHANGE register are

set.

 The ICUTx and ILIMx bits are cleared.

Current Foldback

During an overload or short-circuit condition,

the MP3924 limits the current through the

sense

resistor

controlling

the

external

MOSFET. The MOSFET loses power due to the

rising drain voltage. To reduce power loss and

protect the MOSFET, reduce the current limit

when the drain voltage rises.

MP3924 Datasheet(PDF) 22 Page - Monolithic Power Systems

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