MP3924 datasheet(52/56 Pages) MPS

52 / 56 page

MP3924

– QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

MP3924 Rev. 1.0

MonolithicPower.com

7/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Table 3: ILIM Threshold

ILIM Register Value

ICUT (mA)

425

850 for Class 4

1060 for Class 5

In automatic mode, the bits are set to 0 for

Class 0~3 results, or they are set to 1 for Class

4 and Class 5 based on the classification result.

Design Example

Table 4 shows a design example following the

application guidelines.

Table 4: Design Example

VIN

44V to 57V

VOUT

0V to 57V

POUT

4 x 0W to 30W

Figure 23 on page 53 shows the detailed

application

schematic.

The

Typical

Performance Characteristics section on page

15 shows the typical performance and circuit

waveforms. For more device applications, refer

to the related evaluation board datasheet(s).

PCB Layout Guidelines

Efficient PCB layout is critical, as poor layout

can result in reduced performance, resistive

loss, and system instability. For the best results,

refer to Figure 22 and follow the guidelines

below:

1. Place the current-sense resistor close to the

IC.

optimize

accuracy,

place

the

SENSE1~4 pins and the SGND1~2 pins

close to the current-sense resistor. This

minimizes the impact of the PCB trace

resistance.

2. Kelvin connect the top of R1A

–R1D to the

SENSE1~4 pins. Kelvin connect the bottom

of R1A and R1B to SGND1, then Kelvin

connect R1C and R1D to SGND2.

3. Place the input capacitor (C1B) as close to

the VIN and PGND pins as possible.

4. Place the VCC capacitor (C3) as close to

the VCC and DGND pins as possible.

5. Place the PMAX resistor (R2) as close to

the PMAX and DGND pins as possible.

6. Place a sufficient number of GND vias

under the MP3924 to provide good thermal

dissipation. This also lowers the PCB trace

resistance from the bottom of the current-

sense resistor to PGND.

7. Use a separated DGND and PGND layout.

Connect DGND and PGND under the

package, and between the DGND and

PGND pins.

C1B

C1A

D1D

C2D

Q1D

D1C

C2C

Q1C

D1B

C2B

Q1B

D1A

C2A

Q1A

R1A

R1B

R1D

R1C

VIN

GND

OUT4

OUT3

OUT2

OUT1

Top Layer

Bottom Layer

Vias

Figure 22: Recommended PCB Layout

MP3924 Datasheet(PDF) 52 Page - Monolithic Power Systems

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