MP3924 datasheet(21/56 Pages) MPS

21 / 56 page

MP3924

– QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

MP3924 Rev. 1.0

MonolithicPower.com

7/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

event. During a classification mark event, the

OUTx pins have sink and source current

capability. This means that the output port

voltage can use a 0.1µF capacitor to follow the

OUTx pin

’s regulated voltage.

The classification circuit is disabled when the

classification result is valid and the port output

is powered up.

Start-Up

If the detection and classification results are

valid, the MP3924 ramps up the

port’s output

power. This power is delivered to the PD circuit.

The PENx and PECx bits are then set to

indicate the port status. When the power supply

(VIN) is between 44V and 57V, the MP3924 can

operate from 31V and report over-voltage (OV)

conditions at 65V. If the OUTx pin voltage drops

below 2V, the PGx and PGCx bits are set to

indicate the power good (PG) result.

If the detection is valid but the port does not

start up within 400ms in automatic or semi-

automatic mode, then the port initializes a new

detection cycle.

Four-Channel Sequence

The MP3924 detects, classifies, and starts up

the ports one at a time. Port one is first,

followed by the second, third, and fourth ports.

If no PD is plugged in, the detection process

goes one by one (see Figure 7).

OUT

VIN

80ms

OUT1

OUT2

OUT3

OUT4

OUT1

OUT2

Detection ends

due to open port

Figure 7: No PD on an Output Port

The next port starts detecting within the 80ms

discharge

time

after

the

port

’s

detection cycle ends. Within this 80ms delay,

the port can be discharged below 4V before

detection starts (see Figure 8).

OUT

VIN

80ms

OUT1

OUT2

OUT3

OUT4

OUT1

OUT3

160ms

Figure 8: PD Plug into Port 2

If one of the ports has a PD load and the port

starts up, then the other ports repeat the

detection cycle, from channel one to channel

four. After one channel shuts down, it returns to

its place in the queue (see Figure 9).

OUT

VIN

OUT3

OUT4

OUT1

OUT2

OUT4

OUT1

OUT2

OUT3

Wait for the

next cycle

Internal

Discharge

Figure 9: PD Plug Out from Port 2

Over-Current Protection (OCP)

When the port is powered up, the MP3924

controls the inrush current. As a result, the

output port voltage ramps up smoothly until the

connected PD capacitor charges up to the

power source voltage. In this scenario, the

GATE pin voltage is controlled to limit the input

current (IIN) below 106.25mV / RSENSE.

If the PD capacitor value is too large or the

output port is shorted, the inrush current lasts

for a set time (tINRUSH). After tINRUSH, the port

output power turns off. tINRUSH can be configured

via the TINRUSH bit.

If 106.25mV / RSENSE exceeds ICUT during the

inrush period, the ICUT timer (tICUT) begins

counting. After tICUT, the output turns off. It is

recommended for RSENSE to be 0.25Ω for all

applications. If one port shuts down due to the

start-up inrush current, then the STFx bits are

set to indicate a start failure event.

After start-up, the PGx bits are set to high to

indicate the port

’s output power status. If the

load current exceeds VCUT / RSENSE (VCUT is

MP3924 Datasheet(PDF) 21 Page - Monolithic Power Systems

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