WM8991 datasheet(120/174 Pages) WOLFSON

120 / 174 page

WM8991

Pre-Production

PP, May 2008, Rev 3.1

120

SYSCLK CONTROL

The MCLK_SRC bit is used to select the MCLK source. The source may be either MCLK or

GPIO2/MCLK2. The selected source may also be inverted by setting register bit MCLK_INV. Note

that it is not recommended to change the control bit MCLK_INV while the WM8991 is processing

data as this may lead to clock glitches and signal pop and clicks.

The SYSCLK_SRC bit is used to select the source for SYSCLK. The source may be either the

selected MCLK source or the PLL output. The selected source is divided by the SYSCLK pre-divider

MCLK_DIV to generate SYSCLK. The selected source may also be adjusted by the MCLK_DIV

divider. These register fields are described in Table 65. See “PLL” for more details of the Phase

Locked Loop clock generator.

The WM8991 supports glitch-free MCLK and SYSCLK source selection. When both clock sources

are running and MCLK_SRC or SYSCLK_SRC is modified to select one of these clocks, a glitch-free

clock transition will take place. The de-glitching circuit will ensure that the minimum pulse width will

be no less than the pulse width of the faster of the two clock sources.

When the initial clock source is to be disabled before changing to the new clock source, the

CLK_FORCE bit must also be used to force the clock source transition to take place. In this case,

glitch-free operation cannot be guaranteed.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

MCLK_SRC

MCLK Source Select

0 = MCLK pin

1 = GPIO2/MCLK2 pin

SYSCLK_SRC

SYSCLK Source Select

0 = MCLK (or MCLK2 if MCLK_SRC=1)

1 = PLL output

CLK_FORCE

Forces Clock Source Selection

0 = Existing SYSCLK source (MCLK,

MCLK2 or PLL output) must be active

when changing to a new clock source.

1 = Allows existing MCLK source to be

disabled before changing to a new clock

source.

12:11

MCLK_DIV

[1:0]

00b

SYSCLK Pre-divider. Clock source

(MCLK, MCLK2 or PLL output) will be

divided by this value to generate

SYSCLK.

00 = Divide SYSCLK by 1

01 = Reserved

10 = Divide SYSCLK by 2

11 = Reserved

R7 (07h)

MCLK_INV

MCLK Invert

0 = Master clock (MCLK or MCLK2) not

inverted

1 = Master clock (MCLK or MCLK2)

inverted

Table 65 MCLK and SYSCLK Control

ADC / DAC SAMPLE RATES

The ADC and DAC sample rates are independently selectable, relative to SYSCLK, by setting the

frequency, and according to the selected clocking mode.

Two clocking modes are provided - Normal Mode (AIF_LRCLKRATE = 0) allows selection of the

commonly used sample rates from typical audio system clocking frequencies (eg. 12.288MHz); USB

Mode (AIF_LRCLKRATE = 1) allows many of these sample rates to be generated from a 12MHz

USB clock. Depending on the available clock sources, the USB mode may be used to save power by

supporting 44.1kHz operation without requiring the PLL.

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