WM8991 datasheet(121/174 Pages) WOLFSON

121 / 174 page

Pre-Production

WM8991

PP, May 2008, Rev 3.1

121

The AIF_LRCLKRATE field must be set as described in Table 66 to ensure correct operation of

internal functions according to the SYSCLK / Fs ratio. Table 67 describes the available sample rates

using four different common MCLK frequencies.

In Normal mode, the programmable division set by ADC_CLKDIV must ensure that a 256 * ADC Fs

clock is generated for the ADC DSP. DAC_CLKDIV must ensure that a 256 * DAC Fs clock is

generated for the DAC DSP.

In USB mode, the programmable division set by ADC_CLKDIV must ensure that a 272 * ADC Fs

clock is generated for the ADC DSP. DAC_CLKDIV must ensure that a 272 * DAC Fs clock is

generated for the DAC DSP.

Note that in USB mode, the ADC / DAC sample rates do not match exactly with the commonly used

sample rates (e.g. 44.118 kHz instead of 44.100 kHz). At most, the difference is less than 0.5%.

Data recorded at 44.100 kHz sample rate and replayed at 44.118 kHz will experience a slight (sub

0.5%) pitch shift as a result of this difference. Note also that the USB mode cannot be used to

generate a 48kHz samples rate from a 12MHz MCLK; the PLL should be used in this case.

In low sample rate modes (eg. 8kHz voice), the SNR is liable to be degraded if the typical 64fs DAC

clocking rate is used (see Figure 81). In this case, it may be possible to improve the SNR by raising

the DAC clocking rate by setting the DAC_SDMCLK_RATE register field, causing the DAC clocking

rate to be set equal to SYSCLK/4. The DAC_CLKDIV field must still be set as described above to

derive the correct clock for the DAC DSP. In 8kHz voice applications, in systems where SYSCLK >

256fs (or 272fs when applicable), setting DAC_SDMCLK_RATE will result in the SNR performance

being improved. Note that setting DAC_SDMCLK_RATE will result in an increase in power

consumption.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

7:5

ADC_CLKDIV

[2:0]

000b

ADC Sample Rate Divider

000 = SYSCLK / 1.0

001 = SYSCLK / 1.5

010 = SYSCLK / 2.0

011 = SYSCLK / 3.0

100 = SYSCLK / 4.0

101 = SYSCLK / 5.5

110 = SYSCLK / 6.0

111= Reserved

R7 (07h)

4:2

DAC_CLKDIV

[2:0]

000b

DAC Sample Rate Divider

000 = SYSCLK / 1.0

001 = SYSCLK / 1.5

010 = SYSCLK / 2.0

011 = SYSCLK / 3.0

100 = SYSCLK / 4.0

101 = SYSCLK / 5.5

110 = SYSCLK / 6.0

111= Reserved

DAC_SDMCLK_R

ATE

DAC clocking rate

0 = Normal operation (64fs)

1 = SYSCLK/4

R10 (0Ah)

AIF_LRCLKRATE

LRCLK Rate

0 = Normal mode (256 * fs)

1 = USB mode (272 * fs)

Table 66 ADC / DAC Sample Rate Control

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