WM8991 datasheet(133/174 Pages) WOLFSON

133 / 174 page

Pre-Production

WM8991

PP, May 2008, Rev 3.1

133

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DACR_ENA

(rw)

Right DAC Enable

0 = disabled

1 = enabled

Table 79 Power Management

CHIP RESET AND ID

The device ID can be read back from register 0. Writing to this register will reset the device.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R0 (00h)

Reset / ID

15:0

SW_RESET_

CHIP_ID

[15:0]

(rr)

8990h

Writing to this register resets all registers

to their default state.

Reading from this register will indicate

device family ID 8990h.

Table 80 Chip Reset and ID

SAVING POWER AT HIGHER SUPPLY VOLTAGE

The AVDD supply of the WM8991 can operate between 2.7V and 3.6V. By default, all analogue

circuitry on the device is optimized to run at 3.3V. This set-up is also good for all other supply

voltages down to 2.7V. At lower voltages, performance can be improved by increasing the bias

current. If low power operation is preferred the bias current can be left at the default setting. This is

controlled as shown in Table 81.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R51 (33h)

8:7

VSEL [1:0]

Analogue Bias Optimisation

00 = Reserved

01 = Bias current optimized for AVDD=2.7V

1X = Bias current optimized for AVDD=3.3V

Table 81 Bias Optimisation

WM8991 Datasheet(PDF) 133 Page - Wolfson Microelectronics plc

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