LAN9313 datasheet(147/398 Pages) SMSC

147 / 398 page

Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

SMSC LAN9313/LAN9313i

147

Revision 1.2 (04-08-08)

DATASHEET

13.1

System Control and Status Registers

The System CSR’s are directly addressable memory mapped registers with a base address offset

range of 050h to 2DCh. These registers are accessed through the I2C/SPI serial interfaces or the

MIIM/SMI serial interface. For more information on the various LAN9313/LAN9313i modes and their

corresponding address configurations, see Section 2.3, "Modes of Operation," on page 23.

Table 13.1 lists the System CSR’s and their corresponding addresses in order. All system CSR’s are

reset to their default value on the assertion of a chip-level reset.

The System CSR’s can be divided into 8 sub-categories. Each of these sub-categories contains the

System CSR descriptions of the associated registers. The register descriptions are categorized as

follows:

Section 13.1.1, "Interrupts," on page 151

Section 13.1.2, "GPIO/LED," on page 155

Section 13.1.3, "EEPROM," on page 160

Section 13.1.4, "IEEE 1588," on page 164

Section 13.1.5, "Switch Fabric," on page 192

Section 13.1.6, "PHY Management Interface (PMI)," on page 207

Section 13.1.7, "Virtual PHY," on page 209

Section 13.1.8, "Miscellaneous," on page 224

Table 13.1 System Control and Status Registers

ADDRESS

OFFSET

SYMBOL

000h - 04Ch

RESERVED

Reserved for Future Use

050h

ID_REV

Chip ID and Revision Register, Section 13.1.8.1

054h

IRQ_CFG

Interrupt Configuration Register, Section 13.1.1.1

058h

INT_STS

Interrupt Status Register, Section 13.1.1.2

05Ch

INT_EN

Interrupt Enable Register, Section 13.1.1.3

060h

RESERVED

Reserved for Future Use

064h

BYTE_TEST

Byte Order Test Register, Section 13.1.8.2

068h - 070h

RESERVED

Reserved for Future Use

074h

HW_CFG

Hardware Configuration Register, Section 13.1.8.3

078h - 088h

RESERVED

Reserved for Future Use

08Ch

GPT_CFG

General Purpose Timer Configuration Register,

Section 13.1.8.4

090h

GPT_CNT

General Purpose Timer Count Register, Section 13.1.8.5

094h - 098h

RESERVED

Reserved for Future Use

09Ch

FREE_RUN

Free Running Counter Register, Section 13.1.8.6

0A0h

RESERVED

Reserved for Future Use

0A4h

PMI_DATA

PHY Management Interface Data Register,

Section 13.1.6.1

0A8h

PMI_ACCESS

PHY Management Interface Access Register,

Section 13.1.6.2

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