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XC2000 Datasheet(PDF) 105 Page - Infineon Technologies AG |
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XC2000 Datasheet(HTML) 105 Page - Infineon Technologies AG |
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105 / 729 page ![]() XC2000 Derivatives Peripheral Units (Vol. 2 of 2) Analog to Digital Converter Preliminary User’s Manual 16-11 V1.0, 2007-06 ADC, UM_V0.1D6 16.1.8 Electrical Models Each conversion of an analog input voltage into a digital value consists of two consecutive phases. During the sample phase, the input voltage is sampled and prepared for the following conversion phase. A simplified model for the sample phase describes the input signal path, whereas a second simplified model for the conversion phase is related to the reference voltage handling. 16.1.8.1 Input Signal Path The ADC kernel in the XC2000 is based on one switched capacitor field for measurement with a total capacity represented by CAIN and a small static capacitor at each input pin. During the sample phase, the capacitor field CAIN is connected to one of the analog input CHx via an input multiplexer. The multiplexer is modeled by ideal switches and series resistors RAIN. Only the switch to the selected analog input is closed during the sample phase. During the conversion phase or while no conversion is running (ADC is idle), all switches are open. The voltage at the analog input channel CHx is represented by VAINx. Figure 16-4 Signal Path Model A simplified model for the analog input signal path is given in Figure 16-4. An analog voltage source (value VS) with an internal impedance of REXT delivers the analog input that should be converted. During the sample phase the corresponding switch is closed and the capacitor field CAIN is charged. Due to the low-pass behavior of the resulting RC combination, the voltage VC to be actually converted does not immediately follow VS. The value REXT of the analog voltage source and the desired precision of the conversion strongly define the required length of the sample phase. To reduce the influence of R REXT and to filter input noise, it is recommended to introduce ADC_signal_path_model ADC kernel C AIN R AIN V AGND CHx CH0 CH15 C EXT V AINx R EXT V S V C |
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