SH7021 datasheet(358/509 Pages) RENESAS

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13.1.3

Input/Output Pins

Table 13.1 summarizes the SCI pins by channel.

Table 13.1

SCI Pins

Channel

Pin Name

Abbreviation

Input/Output

Function

Serial clock pin

SCK0

Input/output

SCI0 clock input/output

Receive data pin

RxD0

Input

SCI0 receive data input

Transmit data pin

TxD0

Output

SCI0 transmit data output

Serial clock pin

SCK1

Input/output

SCI1 clock input/output

Receive data pin

RxD1

Input

SCI1 receive data input

Transmit data pin

TxD1

Output

SCI1 transmit data output

13.1.4

Table 13.2 summarizes the SCI internal registers. These registers select the communication mode

(asynchronous or clocked synchronous), specify the data format and bit rate, and control the

transmitter and receiver sections.

Table 13.2

Registers

Channel

Address*1

Name

Abbreviation

R/W

Initial

Value

Access

size

H'05FFFEC0

Serial mode register

SMR0

R/W

H'00

8, 16

H'05FFFEC1

Bit rate register

BRR0

R/W

H'FF

8, 16

H'05FFFEC2

Serial control register

SCR0

R/W

H'00

8, 16

H'05FFFEC3

Transmit data register

TDR0

R/W

H'FF

8, 16

H'05FFFEC4

Serial status register

SSR0

R/(W)*2

H'84

8, 16

H'05FFFEC5

Receive data register

RDR0

H'00

8, 16

H'05FFFEC8

Serial mode register

SMR1

R/W

H'00

8, 16

H'05FFFEC9

Bit rate register

BRR1

R/W

H'FF

8, 16

H'05FFFECA

Serial control register

SCR1

R/W

H'00

8, 16

H'05FFFECB

Transmit data register

TDR1

R/W

H'FF

8, 16

H'05FFFECC Serial status register

SSR1

R/(W)*2

H'84

8, 16

H'05FFFECD Receive data register

RDR1

H'00

8, 16

Notes: 1. Only the values of bits A27–A24 and A8-A0 are valid; bits A23–A9 are ignored. For

details on the register addresses, see section 8.3.5, Description of Areas.

2. Write 0 to clear flags.

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