SH7021 datasheet(359/509 Pages) RENESAS

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RENESAS 344

13.2

13.2.1

Receive Shift Register

The receive shift register (RSR) receives serial data. Data input at the RxD pin are loaded into the

RSR in the order received, LSB (bit 0) first. In this way the SCI converts received data to parallel

form. When one byte has been received, it is automatically transferred to the receive data register

(RDR). The CPU cannot read or write the RSR directly.

Bit:

Bit name:

R/W:

—

13.2.2

Receive Data Register

The receive data register (RDR) stores serial receive data. The SCI completes the reception of one

byte of serial data by moving the received data from the receive shift register (RSR) into the RDR

for storage. The RSR is then ready to receive the next data. This double buffering allows the SCI

to receive data continuously.

The CPU can read but not write the RDR. The RDR is initialized to H'00 by a reset or in standby

mode.

Bit:

Bit name:

Initial value:

R/W:

13.2.3

Transmit Shift Register

The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the

transmit data register (TDR) into the TSR, then transmits the data serially from the TxD pin, LSB

(bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data

from the TDR into the TSR and starts transmitting again. If the TDRE bit of the SSR is 1,

however, the SCI does not load the TDR contents into the TSR. The CPU cannot read or write the

TSR directly.

Bit:

Bit name:

R/W:

—

SH7021 Datasheet(PDF) 359 Page - Renesas Technology Corp