 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
R8C/15 Datasheet(PDF) 149 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
R8C/15 Datasheet(HTML) 149 Page - Renesas Technology Corp |
|
|
149 / 277 page  R8C/14 Group, R8C/15 Group 14. Serial Interface Rev.2.10 Jan 19, 2006 Page 137 of 253 REJ09B0164-0210 Figure 14.9 Transmit Timing in UART Mode Transfer Clock D0 TE Bit in U0C1 Register TXD0 Set to “0” when interrupt request is acknowledged, or set by a program • Transmit Timing When Transfer Data is 8-Bit Long (parity enabled, 1 stop bit) Write data to U0TB register TC D1 D2 D3 D4 D5 D6 D7 P SP TC=16 (n + 1) / fj or 16 (n + 1) / fEXT fj: Frequency of U0BRG count source (f1, f8, f32) fEXT: Frequency of U0BRG count source (external clock) n: Setting value to U0BRG register The above timing diagram applies to the following conditions: • PRYE bit in U0MR register = 1 (parity enabled) • STPS bit in U0MR register = 0 (1 stop bit) • U0IRS bit in UCON register = 1 (an interrupt request is generated when transmit completes) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 ST Start bit Parity bit Stop pulsing because the TE bit is set to “0” D0 TXD0 Write data to U0TB register Transfer from U0TB register to UART0 transmit register TC D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 ST TI Bit in U0C1 Register “1” “0” “1” “0” “1” “0” “1” “0” TXEPT Bit in U0C0 Register IR Bit S0TIC Register Stop bit • Transmit Timing When Transfer Data is 9-Bit Long (parity disabled, 2 stop bits) “1” “0” Stop bit Stop bit Start bit Transfer Clock TE Bit in U0C1 Register TI Bit in U0C1 Register TXEPT Bit in U0C0 Register IR Bit in S0RIC Register “1” “0” “1” “0” “1” “0” Transfer from U0TB register to UART0 transmit register TC=16 (n + 1) / fj or 16 (n + 1) / fEXT fj: Frequency of U0BRG count source (f1, f8, f32) fEXT: Frequency of U0BRG count source (external clock) n: Setting value to U0BRG register Set to “0” when interrupt request is acknowledged, or set by a program The above timing diagram applies to the following conditions: • PRYE bit in U0MR register = 0 (parity disabled) • STPS bit in U0MR register = 1 (2 stop bits) • U0IRS bit in UCON register = 0 (an interrupt request is generated when transmit buffer is empty) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
