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R8C/15 Datasheet(PDF) 208 Page - Renesas Technology Corp |
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R8C/15 Datasheet(HTML) 208 Page - Renesas Technology Corp |
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208 / 277 page ![]() R8C/14 Group, R8C/15 Group 18. Flash Memory Version Rev.2.10 Jan 19, 2006 Page 196 of 253 REJ09B0164-0210 18.3.2 ROM Code Protect Function The ROM code protect function disables to read and change the internal flash memory by the OFS register in parallel I/O mode. Figure 18.4 shows the OFS Register. The ROM code protect function is enabled by writing “0” to the ROMCP1 bit and “1” to the ROMCR bit and disables to read and change the internal flash memory. Once the ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or standard serial I/O mode. Figure 18.4 OFS Register Option Function Select Register (1) Symbol Address Before Shipment OFS 0FFFFh FFh(2) Bit Symbol Bit Name Function RW Reserved Bit NOTES : 1. 2. The OFS register is on the flash memory. Write to the OFS register w ith a program. CSPROINI Count Source Protect Mode After Reset Select Bit 0 : Count source protect mode after reset enabled 1 : Count source protect mode after reset disabled RW — (b6-b4) Reserved Bit Set to “1” RW ROMCP1 ROM Code Protect Bit 0 : ROM code protect enabled 1 : ROM code protect disabled RW ROMCR ROM Code Protect Disabled Bit 0 : ROM code protect disabled 1 : ROMCP1enabled RW Set to “1” RW WDTON Watchdog Timer Start Select Bit 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset RW 1 — (b1) 111 If the block including the OFS register is erased, “FFh” is set to the OFS register. b7 b6 b5 b4 b3 b2 b1 b0 |
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