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R8C/15 Datasheet(PDF) 212 Page - Renesas Technology Corp

Part # R8C/15
Description  16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / R8C/Tiny SERIES
PDF  277 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R8C/15 Datasheet(HTML) 212 Page - Renesas Technology Corp

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R8C/14 Group, R8C/15 Group
18. Flash Memory Version
Rev.2.10
Jan 19, 2006
Page 200 of 253
REJ09B0164-0210
18.4.2.10 FMR40 bit
The erase-suspend function is enabled by setting the FMR40 bit to “1” (enable).
18.4.2.11 FMR41 bit
In EW0 mode, the microcomputer enters erase-suspend mode when setting the FMR41 bit to “1” by a
program. The FMR41 bit is automatically set to “1” (requests erase-suspend) when an interrupt
request of an enabled interrupt is generated in EW1 mode, and then the microcomputer enters erase-
suspend mode.
Set the FMR41 bit to “0” (erase restart) when the auto-erase operation restarts.
18.4.2.12 FMR46 bit
The FMR46 bit is set to “0” (disable reading) during auto-erase execution and set to “1” (enables
reading) in erase-suspend mode. Do not access to the flash memory while this bit is set to “0”.
Figure 18.5
FMR0 Register
Flash Memory Control Register 0
Symbol
Address
After Reset
FMR0
01B7h
00000001b
Bit Symbol
Bit Name
Function
RW
RY/BY
____
Status Flag
NOTES :
1.
2.
3.
4.
5.
6.
FMR07
b3 b2 b1 b0
0
0 : Disables rew rite
1 : Enables rew rite
Flash Memory Stop Bit(3, 5)
0 : Enables flash memory operation
1 : Stops flash memory
(Enters low -pow er consumption state
and flash memory is reset)
FMR01
Block 0, 1 Rew rite Enable Bit(2, 6)
0 : Busy (During w riting or erasing)
1 : READY
CPU Rew rite Mode Select Bit(1)
—
(b5-b4)
FMR00
FMSTP
b7 b6 b5 b4
0
FMR02
RW
RW
0 : CPU rew rite mode disabled
1 : CPU rew rite mode enabled
RO
Reserved Bit
Set to “0”
RW
0 : Completed successfully
1 : Terminated by error
RW
RO
RO
When setting the FMR01 bit to “0” (CPU rew rite mode disabled), the FMR02 bit is set to “0” (disables rew rite).
This bit is set to “0” by executing the clear status command.
This bit is enabled w hen the FMR01 bit is set to “1” (CPU rew rite mode). When the FMR01 bit is set to “0” and w riting
“1” to the FMSTP bit, the FMSTP bit is set to “1”. The flash memory does not enter low -pow er
consumption stat nor is reset.
FMR06
When setting this bit to “1”, set to “1” immediately after setting it first to “0”. Do not generate an interrupt betw een
setting the bit to “0” and setting it to “1”. Enter read array mode and set this bit to “0”.
Set this bit to “1” immediately after setting this bit first to “0” w hile the FMR01 bit is set to “1”.
Do not generate an interrupt betw een setting the bit to “0” and setting it to “1”.
Set this bit by a program in a space other than the flash memory.
Program Status Flag(4)
0 : Completed successfully
1 : Terminated by error
Erase Status Flag(4)



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