R8CSLASH15 datasheet(213/277 Pages) RENESAS

213 / 277 page

R8C/14 Group, R8C/15 Group

18. Flash Memory Version

Rev.2.10

Jan 19, 2006

Page 201 of 253

REJ09B0164-0210

Figure 18.6

FMR1 and FMR4 Registers

Flash Memory Control Register 1

Symbol

Address

After Reset

FMR1

01B5h

1000000Xb

Bit Symbol

Bit Name

Function

NOTES :

FMR16

Block 1 Rew rite Disable Bit(2,3)

When setting this bit to “1”, set to “1” immediately after setting it first to “0” w hile the FMR01 bit is set to “1” (CPU

rew rite mode enable) . Do not generate an interrupt betw een setting the bit to “0” and setting it to “1”.

This bit is set to “0” by setting the FMR01 bit to “0” (CPU rew rite mode disabled).

Reserved Bit

Set to “1”

When the FMR01 bit is set to “1” (CPU rew rite mode enabled), the FMR15 and FMR16 bits can be w ritten.

When setting this bit to “0”, set to “0” immediately after setting it first to “1”.

When setting this bit to “1”, set it to “1”.

—

(b7)

Reserved Bit

0 : Enables rew rite

1 : Disables rew rite

FMR15

—

(b0)

Reserved Bit

When read, its content is indeterminate.

EW1 Mode Select Bit(1, 2)

0 : EW0 mode

1 : EW1 mode

Block 0 Rew rite Disable Bit(2,3)

0 : Enables rew rite

1 : Disables rew rite

b7 b6 b5 b4

b3 b2

Set to “0”

b1 b0

FMR11

—

(b4-b2)

Flash Memory Control Register 4

Symbol

Address

After Reset

FMR4

01B3h

01000000b

Bit Symbol

Bit Name

Function

NOTES :

—

(b7)

Read Status Flag

Reserved Bit

Set to “0”

FMR46

Erase-Suspend Function

Enable Bit(1)

0 : Disables reading

1 : Enables reading

Reserved Bit

0 : Disable

1 : Enable

Erase-Suspend Request

Bit(2)

0 : Erase restart

1 : Erase-suspend request

b7 b6 b5 b4

—

(b5-b2)

00 0

FMR40

When setting this bit to “1”, set to “1” immediately after setting it first to “0”. Do not generate an interrupt betw een

setting the bit to “0” and setting it to “1”.

This bit is enabled w hen the FMR40 bit is set to “1” (enable) and this bit can be w ritten during the period betw een

issuing an erase command and completing an erase (This bit is set to “0” during the periods other than above).

In EW0 mode, this can be set to “0” and “1” by a program.

In EW1 mode, this bit is automatically set to “1” if a maskable interrupt is generated during an erase

operation w hile the FMR40 bit is set to “1”. Do not set this bit to “1” by a program (“0” can be w ritten).

b3 b2

Set to “0”

b1 b0

FMR41

R8C/15 Datasheet(PDF) 213 Page - Renesas Technology Corp

R8C/15 Datasheet(HTML) 213 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL