R8CSLASH15 datasheet(209/277 Pages) RENESAS

209 / 277 page

R8C/14 Group, R8C/15 Group

18. Flash Memory Version

Rev.2.10

Jan 19, 2006

Page 197 of 253

REJ09B0164-0210

18.4

CPU Rewrite Mode

In CPU rewrite mode, user ROM area can be rewritten by executing software commands from the CPU.

Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on a board

without using such as a ROM programmer. Execute the program and block erase commands only to

each block in user ROM area.

When an interrupt request is generated during an erase operation in CPU rewrite mode, the flash

module contains an erase-suspend function which performs the interrupt process after the erase

operation is halted temporarily. During the erase-suspend, user ROM area can be read by a program.

CPU rewrite mode contains erase write 0 mode(EW0 mode) and erase write 1 mode(EW1 mode). Table

18.3 lists the Differences between EW0 Mode and EW1 Mode.

NOTES:

1. When setting the FMR02 bit in the FMR0 register to “1” (rewrite enables) and rewriting Block 0 is

enabled by setting the FMR15 bit in the FMR1 register to “0” (rewrite enables). Rewriting Block 1 is

enabled by setting the FMR16 bit to “0” (rewrite enables).

Table 18.3

Differences between EW0 Mode and EW1 Mode

Item

EW0 Mode

EW1 Mode

Operating Mode

Single chip mode

Area in which rewrite

control program can be

located

User ROM area

Area in which rewrite

control program can be

executed

Necessary to transfer to any areas

other than the flash memory (e.g.,

RAM) before executing

Executing directly on user ROM area

is possible

Area which can be

rewritten

User ROM area

However, other than the blocks

which contain a rewrite control

program(1)

Software Command

Restriction

None

• Program, block erase command

Disable to execute on any block

which contains a rewrite control

program

• Disables to execute the read status

Mode after Program or

Erase

Read status register mode

Read array mode

CPU Status during Auto-

Write and Auto-Erase

Operating

Hold state (I/O ports hold state

before the command is executed)

Flash Memory Status

Detection

• Read the FMR00, FMR06, and

FMR07 bits in the FMR0 register by

a program

• Execute the read status register

command and read the SR7, SR5,

and SR4 bits in the status register.

Read the FMR00, FMR06, and

FMR07 bits in the FMR0 register by a

program

Condition for Transition to

Erase-Suspend

Set the FMR40 and FMR41 bits in

the FMR4 register to “1” by a

program.

The FMR40 bit in the FMR4 register

is set to “1” and the interrupt request

of the enabled maskable interrupt is

generated

CPU Clock

5MHz or below

No restriction to the following (clock

frequency to be used)

R8C/15 Datasheet(PDF) 209 Page - Renesas Technology Corp

R8C/15 Datasheet(HTML) 209 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL