R8CSLASH15 datasheet(210/277 Pages) RENESAS

210 / 277 page

R8C/14 Group, R8C/15 Group

18. Flash Memory Version

Rev.2.10

Jan 19, 2006

Page 198 of 253

REJ09B0164-0210

18.4.1

EW0 Mode

The microcomputer enters CPU rewrite mode and software commands can be acknowledged by

setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled). In this case, since the

FMR11 bit in the FMR1 register is set to “0”, EW0 mode is selected.

Use software commands to control a program and erase operations. The FMR0 register or the status

When entering an erase-suspend, set the FMR40 bit to “1” (enables erase-suspend) and the FMR41

bit to “1” (requests erase-suspend). Wait for td(SR-ES) and ensure that the FMR46 bit is set to “1”

(enables reading) before accessing the user ROM area. The auto-erase operation restarts by setting

the FMR41 bit to “0” (erase restarts).

18.4.2

EW1 Mode

The microcomputer enters EW1 mode by setting the FMR11 bit to “1” (EW1 mode) after setting the

FMR01 bit to “1” (CPU rewrite mode enabled).

The FMR0 register can determine status when program and erase operation complete. Do not

execute the read status register command in EW1 mode.

To enable the erase-suspend function, execute the block erase command after setting the FMR40 bit

to “1” (enables erase-suspend). The interrupt to enter an erase-suspend should be in interrupt

enabled status. After passing td(SR-ES) since the block erase command is executed, an interrupt

request is acknowledged.

When an interrupt request is generated, the FMR41 bit is automatically set to "1" (requests erase-

suspend) and the auto-erase operation is halted. If the auto-erase operation does not complete

(FMR00 bit is “0”) when the interrupt process completes, the auto-erase operation restarts by setting

the FMR41 bit to “0” (erase restarts)

R8C/15 Datasheet(PDF) 210 Page - Renesas Technology Corp