32182 datasheet(64/755 Pages) RENESAS

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3-5

ADDRESS SPACE

32182 Group User’s Manual (Rev.1.0)

3.2 Operation Modes

The microcomputer is placed in one of the following modes depending on how CPU operation mode is set by

MOD0 and MOD1 pins. The operation mode used for rewriting the internal flash memory is described separately

in Section 6.5, “Programming the Internal Flash Memory.”

Table 3.2.1 Operation Mode Settings

MOD0

MOD1 (Note 1)

Operation mode (Note 2)

VSS

Single-chip mode

VSS

VCCE

External extension mode

VCCE

VSS

Processor mode (FP = VSS)

VCCE

Reserved (use inhibited)

Note 1: Connect VCCE and VSS to the VCCE input power supply and ground, respectively.

Note 2: For the operation mode used to rewrite the internal flash memory (FP = VCCE) which is not shown in the above

table, see Section 6.5, “Programming the Internal Flash Memory.”

The internal ROM and extended external areas are located differently depending on how operation mode is set.

(All other areas in the address space are located the same way.) The diagram below shows how the internal ROM

and extended external areas are mapped into the address space in each operation mode. (For flash rewrite mode,

see Section 6.5, “Programming the Internal Flash Memory.”)

3.2 Operation Modes

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