32182 datasheet(33/755 Pages) RENESAS

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1-6

OVERVIEW

32182 Group User’s Manual (Rev.1.0)

1.2 Block Diagram

Table 1.2.1 Features of the 32182 (1/2)

Functional Block

Features

M32R-FPU CPU core

• Implementation: Five-stage pipelined instruction processing (processed in six stages when

performing floating-point arithmetic)

• Internal 32-bit structure of the core

• Register configuration

General-purpose registers: 32 bits × 16 registers

Control registers: 32 bits × 6 registers

• Instruction set

16 and 32-bit instruction formats

100 discrete instructions and six addressing modes

• Internal multiplier/accumulator (32 bits × 16 bits + 56 bits)

• Internal single-precision floating-point arithmetic unit (FPU)

RAM

• Capacity: 64 Kbytes, accessible with zero wait state

• The internal RAM can be accessed for reading or rewriting data from the outside independently of

the M32R-FPU by using the Real-Time Debugger, without ever causing the CPU performance to

decrease.

Flash memory

• Capacity

M32182F3: 384 Kbytes, 1M32182F8: 1 Mbyte

• One-wait access

• Durability: Rewritable 100 times

Bus specification

• Fundamental bus cycle: 12.5 ns (when f(CPUCLK = 80 MHz)

• Logical address space : 4 Gbytes linear

• Internal bus specification : Internal 32-bit data bus (for CPU <-> internal flash memory and RAM access)

(or accessed in 64 bits when accessing the internal flash memory for

instructions)

: Internal 16-bit data bus (for internal peripheral I/O access)

• Extended external area: Maximum 3 Mbytes (1 Mbytes × 3 blocks during external

extension mode)

• External data address: 20-bit address

• External data bus: 16-bit data bus

• Shortest external bus access: 1 BCLK period during read, 1 BCLK period during write

Multijunction timer (MJT)

• 37-channel multi-functional timer

16-bit output related timer × 11 channels, 16-bit input/output related timer × 10 channels,

16-bit input related timer × 8 channels, 32-bit input related timer × 8 channels

• Flexible timer configuration is possible by interconnecting these timer channels.

• Interrupt request: Counter underflow or overflow and rising or falling or both edges or high or low level

from the TIN pin (These can be used as external interrupt inputs irrespective of timer operation.)

• DMA transfer request: Counter underflow or overflow and rising or falling or both edges or high or

low level from the TIN pin (These can be used as external DMA transfer request inputs

irrespective of timer operation.)

DMAC

• Number of channels: 10

• Transfers between internal peripheral I/O’s or internal RAM’s or between internal peripheral I/O

and internal RAM are supported.

• Capable of advanced DMA transfers when used in combination with internal peripheral I/O

• Transfer request: Software or internal peripheral I/O (A-D converter, MJT, serial I/O or CAN)

• DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a

transfer on another channel.)

• Interrupt request: DMA transfer counter register underflow

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