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32182 Datasheet(PDF) 102 Page - Renesas Technology Corp |
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32182 Datasheet(HTML) 102 Page - Renesas Technology Corp |
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102 / 755 page ![]() 4 4-7 EIT 32182 Group User’s Manual (Rev.1.0) 4.4 EIT Processing Mechanism The EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/ Os. It also has the backup registers for the PC and PSW (the BPC register and the BPSW field of the PSW register). The EIT processing mechanism is shown below. 4.4 EIT Processing Mechanism Figure 4.4.1 EIT Processing Mechanism Interrupt controller (ICU) SBI EI Internal peripheral I/Os RESET# RI AE, RIE, FPE, TRAP IE flag (PSW) M32R CPU core SBI# Low High Priority SBI EI RI M32R/ECU PSW register PSW BPSW BPC register PC register |
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