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ST7787 Datasheet(PDF) 33 Page - Sitronix Technology Co., Ltd. |
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ST7787 Datasheet(HTML) 33 Page - Sitronix Technology Co., Ltd. |
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33 / 217 page  ST7787 V1.7 2008.04.18 33 8.3 Serial interface characteristics (3-line serial) CSX VIH VIL TCHW TCSH TOH TCSS SCL SDA SDA (DOUT) TSCC TSCYCW/TSCYCR TACC VIH VIL VIH VIL VIH VIL VIH VIL TSDS TSDH TSHW/TSHR TSLW/TSLR Fig. 8.3.1 3-line serial interface timing Signal Symbol Parameter Min Max Unit Description TCSS Chip select setup time 60 ns TCSH Chip select hold time 60 ns TSCC Chip select setup time 20 ns CSX TCHW Chip select setup time 40 ns TSCYCW Serial clock cycle (Write) 66 ns TSHW SCL “H” pulse width (Write) 20 ns TSLW SCL “L” pulse width (Write) 20 ns TSCYCR Serial clock cycle (Read) 150 ns TSHR SCL “H” pulse width (Read) 60 ns SCL TSLR SCL “L” pulse width (Read) 60 ns TSDS Data setup time 10 ns TSDH Data hold time 10 ns TACC Access time 10 ns SDA (DIN) (DOUT) TOH Output disable time 15 ns For maximum CL=30pF For minimum CL=8pF Table 8.3: 3-line Serial Interface Characteristics Note 1: VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70℃ Note 2: The rising time and falling time (Tr, Tf) of input signal and fall time are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. 8.4 Vertical synchronizing signal timing characteristic Fig. 8.4 Vertical synchronizing signal timing Signal Symbol Parameter Min Max Unit Description tVCYC VSYNC Cycle 1F+2H - - tVLW VSYNC Pulse L Width 1H 1F-1H - VSYNC tVHW VSYNC Pulse H Width 3H - -Standing up standing fall time of the input signal(tr,tf) is provided for by 15ns or less. -The signal level is provided for based on 30% and 70% of VDDI-DGND -This is provided for while external VSYNC is synchronizing. -F indicates the time of one frame in internal synchronizition. -H indicates the time in internal synchronizition for one line. |
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