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ST7787 Datasheet(PDF) 96 Page - Sitronix Technology Co., Ltd. |
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ST7787 Datasheet(HTML) 96 Page - Sitronix Technology Co., Ltd. |
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96 / 217 page ![]() ST7787 V1.7 2008.04.18 96 9.17.3 Reset Timing Table 9.18.3.1 Reset input timing VSS=0V, VDDI=1.65V to 1.95V, VDD=2.45V to 2.9V,Ta = -30 to 70 ) ℃ Symbol Parameter Related Pins MIN TYP MAX Note Unit tRESW *1) Reset low pulse width RESX 30 - - - us tREST *2) Reset complete time - 120 - - ms Note 1) Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below. Note 2. During the resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode) and then return to Default condition for H/W reset. Note 3. During Reset Complete Time, ID2 and VCOMOF value in OTP will be latched to internal register during this period. This loading is done every time when there is H/W reset complete time (tREST) within 120ms after a rising edge of RESX. Note 4. Spike Rejection also applies during a valid reset pulse as shown below: |
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