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ST7787 Datasheet(PDF) 65 Page - Sitronix Technology Co., Ltd. |
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ST7787 Datasheet(HTML) 65 Page - Sitronix Technology Co., Ltd. |
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65 / 217 page ![]() ST7787 V1.7 2008.04.18 65 9.9.6 RGB Interface Timing Diagram 9.9.6.1 General Timings for RGB I/F Fig. 9.9.6 General timing of RGB interface Table 9.9.6.1 General Timing for RGB I/F Specification Item Symbol Condition Min Type. Max Unit Pixel low pulse width TPCLKLT 12 ns Pixel high pulse width TPCLKHT 12 ns Vertical Sync. set-up time TVSST 15 ns Vertical Sync. hold time TVSSHT 15 ns Horizontal Sync. set-up time THSST 15 ns Horizontal Sync. hold time TVSSHT 15 ns Data Enable set-up time TDEST 15 ns Data Enable hold time TDEHT 15 ns Data set-up time TDST 15 ns Data hold time TDHT 15 ns Note 1: VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 ℃ (to +85℃ no damage) Note 2: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Note 3. Data lines can be set to “High” or “Low” during blanking time – Don’t care. Note 4. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. Note 5. HP is multiples of eight PCLK. |
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