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ST7787 Datasheet(PDF) 40 Page - Sitronix Technology Co., Ltd. |
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ST7787 Datasheet(HTML) 40 Page - Sitronix Technology Co., Ltd. |
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40 / 217 page ![]() ST7787 V1.7 2008.04.18 36 9.4 Serial interface The selection of this interface is done by IM2. See the Table 9.4.1. Table 9.4.1 Serial Interface Type Selection P68 IM2 IM1 IM0 Interface Read back selection ‘-’ 0 ‘-’ ‘-’ 3-line Serial interface Via the read instruction (8-bit, 24-bit and 32-bit read parameter) The serial interface is a 3-lines/ 9-bits bi-directional interface for communication between the micro controller and the LCD driver chip. The 3-lines serial use: CSX (chip enable), SCL (serial clock) and SDA (serial data input/output) Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no communication is necessary. 9.4.1 Command Write Mode The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-lines serial data packet contains a control bit D/CX and a transmission byte is transfrerred by the D/CX pin. If D/CX is “low”, the transmission byte is interpreted as a command byte. If D/CX is “high”, the transmission byte is stored in the display data RAM (Memory write command), or command register as parameter. Any instruction can be sent in any order to the DRIVER. The MSB is transmitted first. The serial interface is initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission. Fig. 9.4.1 Serial interface data Stream format When CSX is “high”, SCL clock is ignored. During the high time of CSX the serial interface is initialized. At the falling edge of CSX, SCL can be high or low (see Fig 6.1.1.2). SDA is sampled at the rising edge of CSX. D/CX indicates, whether the byte is command code (D/CX=’0’) or parameter/RAM data (D/CX=’1’). It is sampled when first rising edge of SCL (3-lines serial interface) . If CSX stays low after the last bit of command/data byte, the serial interface expects the D/CX bit (3-lines serial interface) at the next rising edge of SCL. Fig. 9.4.2 3-line serial interface write protocol (write to register with control bit in transmission) D/CXD7 D6 D5 D4 D3 D2 D1 D0 D/CXD7 D6 D5 D4 D3 D2 D1 D0 D/CXD7 D6 D5 D4 D3 D2 D1 D0 D/CXD7 D6 D5 D4 D3 D2 D1 D0 MSB LSB Transmission byte (TB) may be a Command or a Data 3-Line Serial Data Stream Format TB TB TB |
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