DAC3482 datasheet(34/79 Pages) TI1

34 / 79 page

DAC3482

SLAS748A

– MARCH 2011 – REVISED JUNE 2011

www.ti.com

– Address: 0x14, Default: 0x0000

Default

Address

Bit

Name

Function

Value

Name

config20

0x14

15:0

phase_ add(15:0)

The phase_add(15:0) value is used to determine the NCO frequency. The two

’s

0x0000

complement formatted value can be positive or negative. Each LSB represents

Fs/(2^32) frequency step.

– Address: 0x15, Default: 0x0000

Default

Address

Bit

Name

Function

Value

Name

config21

0x15

15:0

phase_ add(31:16)

See config20 above.

0x0000

– Address: 0x16, Default: 0x0000

Default

Address

Bit

Name

Function

Value

Name

config22

0x16

15:0

Reserved

Reserved for factory use.

0x0000

– Address: 0x17, Default: 0x0000

Default

Address

Bit

Name

Function

Value

Name

config23

0x17

15:0

Reserved

Reserved for factory use.

0x0000

– Address: 0x18, Default: NA

Default

Address

Bit

Name

Function

Value

Name

config24

0x18

15:13

Reserved

Reserved for factory use.

001

pll_reset

When set, the PLL loop filter (LPF) is pulled down to 0V. Toggle from

‘1’ to ‘0’ to

restart the PLL if an over-speed lock-up occurs. Over-speed can happen when the

process is fast, the supplies are higher than nominal, etc. resulting in the feedback

dividers missing a clock.

pll_ndivsync_ena

When set, the LVDS SYNC input is used to sync the PLL N dividers.

pll_ena

When set, the PLL is enabled. When cleared, the PLL is bypassed.

9:8

Reserved

Reserved for factory use.

7:6

pll_cp(1:0)

PLL pump charge select

MM 00: No charge pump

MM 01: Single pump charge

MM 10: Not used

MM 11: Dual pump charge

5:3

pll_p(2:0)

PLL pre-scaler dividing module control.

001

MM 010: 2

MM 011: 3

MM 100: 4

MM 101: 5

MM 110: 6

MM 111: 7

MM 000: 8

2:0

pll_lfvolt(2:0)

PLL loop filter voltage. This three bit read-only indicator has step size of 0.4125V.

The entire range covers from 0V to 3.3V. The optimal lock range of the PLL will be

from 010 to 101 (i.e. 0.825V to 2.063V). Adjust pll_vco(5:0) for optimal lock range.

Submit Documentation Feedback

Product Folder Link(s): DAC3482

DAC3482 Datasheet(PDF) 34 Page - Texas Instruments

DAC3482 Datasheet(HTML) 34 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL