DAC3482 datasheet(67/79 Pages) TI1

67 / 79 page

GND

CLKVDD

Internal

Digital In

DACCLKN

OSTRN

S0515-01

DACCLKP

OSTRP

SLEEP

250

2 k

DAC3482

www.ti.com

SLAS748A

– MARCH 2011 – REVISED JUNE 2011

Table 10. Example Start-Up Sequence Description (continued)

STEP

READ/WRITE

ADDRESS

VALUE

DESCRIPTION

Sync all the QMC blocks using sif_sync. These blocks can also be synced

Write

0x1F

0x4142

via auto-sync through appropriate register writes.

Write

0x00

0xA19A

Disable clock divider sync.

Disable FIFO data formatter sync. Set sif_sync to

“0” for the next sif_sync

Write

0x1F

0x4148

event.

Write

0x20

0x0000

Disable FIFO input and output pointer sync.

Write

0x18

0x2458

Disable PLL N-dividers sync.

N/A

Set TXENABLE high. Enable data transmission.

LVPECL INPUTS

Figure 80 shows an equivalent circuit for the DAC input clock (DACCLKP/N) and the output strobe clock

(OSTRP/N).

Figure 80. DACCLKP/N and OSTRP/N Equivalent Input Circuit

Figure 81 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential

ECL/PECL source.

Submit Documentation Feedback

Product Folder Link(s): DAC3482

DAC3482 Datasheet(PDF) 67 Page - Texas Instruments

DAC3482 Datasheet(HTML) 67 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL