DAC3482 datasheet(59/79 Pages) TI1

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I Data In

Q Data In

I Data Out

Q Data Out

qmc_offsetI

{–4096, –4095, ..., 4095}

qmc_offsetQ

{–4096, –4095, ..., 4095}

B0165-02

DAC3482

www.ti.com

SLAS748A

– MARCH 2011 – REVISED JUNE 2011

Figure 75. Digital Offset Block Diagram

GROUP DELAY CORRECTION

A complex transmitter system typically is consisted of a DAC, reconstruction filter network, and I/Q modulator.

Besides the gain and phase mismatch contribution, there could also be timing mismatch contribution from each

components. For instance, the timing mismatch could come from the PCB trace length variation between the I

and Q channels and the group delay variation from the reconstruction filter.

This timing mismatch in the complex transmitter system creates phase mismatch that varies linearly with respect

to frequency. To compensate for the I/Q imbalances due to this mismatch, the DAC3482 has group delay

correction block for each DAC channel. Each DAC channel can adjust its delay through grp_delayI(7:0) and

grp_delayq(7:0) in register config46 and config47, respectively. The maximum delay ranges from 30ps to 100ps

and is dependent on DAC sample clock. Contact TI for specific application information. The group delay

correction, along with gain/phase correction, can be useful for correcting imbalances in wide-band transmitter

system.

TEMPERATURE SENSOR

The DAC3482 incorporates a temperature sensor block which monitors the temperature by measuring the

voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation

(SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement

value representing the temperature in degrees Celsius.

The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled

(tsense_sleep = 0 in register config26) a conversion takes place each time the serial port is written or read. The

data is only read and sent out by the digital block when the temperature sensor is read in tempdata(7:0) in

config6. The conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the

data is valid on the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth

SCLK. No other clocks to the chip are necessary for the temperature sensor operation. As a result the

temperature sensor is enabled even when the device is in sleep mode.

In order for the process described above to operate properly, the serial port read from config6 must be done with

an SCLK period of at least 1

μs. If this is not satisfied the temperature sensor accuracy is greatly reduced.

DATA PATTERN CHECKER

The DAC3482 incorporates a simple pattern checker test in order to determine errors in the data interface. The

main cause of failures is setup/hold timing issues. The test mode is enabled by asserting iotest_ena in register

config1. In test mode the analog outputs are deactivated regardless of the state of TXENABLE or sif_texnable in

The data pattern key used for the test is 8 words long and is specified by the contents of iotest_pattern[0:7] in

registers config37 through config44. The data pattern key can be modified by changing the contents of these

registers.

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