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DAC3482 Datasheet(PDF) 63 Page - Texas Instruments

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Part # DAC3482
Description  Dual-Channel, 16-BIT, 1.25 GSPS Digital-to-Analog Converter (DAC)
PDF  79 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC3482 Datasheet(HTML) 63 Page - Texas Instruments

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D[15:0]P/N
FRAMEP/N
•••
•••
T0527-01
DATACLKP/N
(DDR)
I
[15:0]
0
I
[15:0]
1
Q
[15:0]
0
Q
[15:0]
1
Parity Bit for
Data Block N – 1
High
Low
= Odd Parity
= Even Parity
Stop Point for
Data Block N – 1
Start Point for
Data Block N
D[15:0]P/N
FRAMEP/N
DATACLKP/N
(DDR)
I
[15:0]
x
I
[15:0]
y
Q
[15:0]
x
Q
[15:0]
y
Parity Bit for
Data Block N
High
Low
= Odd Parity
= Even Parity
Stop Point for
Data Block N
Start Point for
Data Block N + 1
Data Block N
DAC3482
www.ti.com
SLAS748A
– MARCH 2011 – REVISED JUNE 2011
Since the FRAME signal is used for parity testing in addition to FIFO syncing and frame boundary assignment, it
is mandatory to take some extra steps to avoid device malfunction. If FRAME is used to reset the FIFO pointers
continuously, the block size must be a multiple of 8 samples (each sample corresponding to 16-bits I and 16-bits
Q). In addition since FRAME is used in byte-wide input data mode to establish the frame boundary, the parity
block must be aligned with the data frame boundaries.
Notes: Rising edge of FRAMEP/N indicates the beginning of data block.
Parity bit for the current data block is latched on falling edge of DATACLK after the start point for next data block.
Figure 79. DAC3482 Block Parity Check (Example shown with Word-Wide Mode)
DAC3482 ALARM MONITORING
The DAC3482 includes a flexible set of alarm monitoring that can be used to alert of a possible malfunction
scenario. All the alarm events can be accessed either through the config5 register or through the ALARM pin.
Once an alarm is set, the corresponding alarm bit in register config5 must be reset through the serial interface to
allow further testing. The set of alarms includes the following conditions
Zero check alarm
•
Alarm_from_zerochk. Occurs when the FIFO write pointer has an all zeros pattern. Since the write pointer is a
shift register, all zeros will cause the input point to be stuck until the next sync event. When this happens a
sync to the FIFO block is required.
FIFO alarms
•
alarm_from_fifo. Occurs when there is a collision in the FIFO pointers or a collision event is close.
– alarm_fifo_2away. Pointers are within two addresses of each other.
– alarm_fifo_1away. Pointers are within one address of each other.
– alarm_fifo_collision. Pointers are equal to each other.
Clock alarms
•
clock_gone. Occurs when either the DACCLK or DATACLOCK have been stopped.
– alarm_dacclk_gone. Occurs when the DACCLK has been stopped.
– alarm_dataclk_gone. Occurs when the DATACLK has been stopped.
Pattern checker alarm
•
alarm_from_iotest. Occurs when the input data pattern does not match the pattern key.
PLL alarm
•
alarm_from_pll. Occurs when the PLL is out of lock.
Copyright
© 2011, Texas Instruments Incorporated
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