DAC3482 datasheet(69/79 Pages) TI1

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SDIO

SCLK

SLEEP

TXENABLE

Internal

Digital In

GND

400

100 k

GND

IOVDD

SDENB

RESETB

Internal

Digital In

S0027-03

DAC3482

www.ti.com

SLAS748A

– MARCH 2011 – REVISED JUNE 2011

Table 11. Example LVDS Data Input Levels

Resulting Differential

Resulting Common-Mode

Applied Voltages

Logical Bit Binary

Voltage

Equivalent

VA,B

VCOM

1.4 V

1.0 V

400 mV

1.2 V

1.0 V

1.4 V

-400 mV

1.2 V

0.8 V

400 mV

1.0 V

0.8 V

1.2 V

-400 mV

CMOS DIGITAL INPUTS

Figure 84 shows a schematic of the equivalent CMOS digital inputs of the DAC3482. SDIO, SCLK, SLEEP and

TXENABLE have pull-down resistors while SDENB and RESETB have pull-up resistors internal to the DAC3482.

See the specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to

100k

Ω.

Figure 84. CMOS Digital Equivalent Input

REFERENCE OPERATION

The DAC3482 uses a bandgap reference and control amplifier for biasing the full-scale output current. The

full-scale output current is set by applying an external resistor RBIAS to pin BIASJ. The bias current IBIAS through

resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale

output current equals 64 times this bias current and can thus be expressed as:

IOUTFS = 64 x IBIAS = 64 x (VEXTIO / RBIAS ) / 2

The DAC3482 has a 4-bit coarse gain control coarse_dac(3:0) in the config3 register. Using gain control, the

IOUTFS can be expressed as:

IOUTFS = (coarse_dac + 1)/16 x IBIAS x 64 = (coarse_dac + 1)/16 x (VEXTIO / RBIAS) / 2 x 64

where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of

1.2V. This reference is active when extref_ena =

‘0’ in config27. An external decoupling capacitor CEXT of 0.1 µF

should be connected externally to terminal EXTIO for compensation. The bandgap reference can additionally be

used for external reference operation. In that case, an external buffer with high impedance input should be

applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be

disabled and overridden by an external reference by setting the extref_ena control bit. Capacitor CEXT may hence

be omitted. Terminal EXTIO thus serves as either input or output node.

The full-scale output current can be adjusted from 30 mA down to 10 mA by varying resistor RBIAS, programming

coarse_dac(3:0), or changing the externally applied reference voltage.

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