DAC3482 datasheet(37/79 Pages) TI1

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DAC3482

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SLAS748A

– MARCH 2011 – REVISED JUNE 2011

– Address: 0x1F, Default: 0x1140

Default

Address

Bit

Name

Function

Value

Name

config31

0x1F

15:12

syncsel_mixer(3:0)

Selects the syncing source(s) of the double buffered mixer registers. A

‘1’ in the

0001

bit enables the signal as a sync source. More than one sync source is permitted.

MM Bit 15: sif_sync (via config31)

MM Bit 14: SYNC

MM Bit 13: OSTR

MM Bit 12: Auto-sync from register write

11:8

Reserved

Reserved for factory use.

0001

7:4

syncsel_nco(3:0)

Selects the syncing source(s) of the two NCO accumulators. A

‘1’ in the bit

0100

enables the signal as a sync source. More than one sync source is permitted.

MM Bit 7: sif_sync (via config31)

MM Bit 6: SYNC

MM Bit 5: OSTR

MM Bit 4: FRAME

3:2

syncsel_dataformatter

Selects the syncing source of the data formatter. Unlike the other syncs only

one sync source is allowed.

MM 00: FRAME

MM 01: SYNC

MM 10: No sync

MM 11: No sync

sif_sync

SIF created sync signal. Set to

‘1’ to cause a sync and then clear to ‘0’ to

remove it.

Reserved

Reserved for factory use.

– Address: 0x20, Default: 0x2400

Default

Address

Bit

Name

Function

Value

Name

config32

0x20

15:12

syncsel_fifoin(3:0)

Selects the syncing source(s) of the FIFO input side. A

‘1’ in the bit enables the

0010

signal as a sync source. More than one sync source is permitted.

MM Bit 15: sif_sync (via config31)

MM Bit 14: Always zero

MM Bit 13: FRAME

MM Bit 12: SYNC

11:8

syncsel_fifoout(3:0)

Selects the syncing source(s) of the FIFO output side. A

‘1’ in the bit enables the

0100

signal as a sync source. More than one sync source is permitted.

MM Bit 11: sif_sync (via config31)

MM Bit 10: OSTR

– Dual Sync Sources Mode

MM Bit 9: FRAME

– Single Sync Source mode

MM Bit 8: SYNC

– Single Sync Source mode

7:1

Reserved

Reserved for factory use.

0000

clkdiv_sync_sel

Selects the signal source for clock divider synchronization.

clkdiv_sync_sel

Sync Source

OSTR

FRAME or SYNC, based on syncsel_fifoin source

selection (config32, bit

<15:12>)

– Address: 0x21, Default: 0x0000

Default

Address

Bit

Name

Function

Value

Name

config33

0x21

15:0

Reserved

Reserved for factory use.

0x0000

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