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DAC3482 Datasheet(PDF) 68 Page - Texas Instruments |
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DAC3482 Datasheet(HTML) 68 Page - Texas Instruments |
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68 / 79 page  C 0.1 F AC C 0.1 F AC Differential ECL or (LV)PECL Source + – CLKIN CLKINC S0029-02 100 R 150 T R 150 T GND Internal Digital In IOVDD LVDS Receiver S0516-01 100 LVDS Receiver DAC3482 GND B0459-01 100 V B V B V A V A 1.4 V 1 V 400 mV 0 V –400 mV 1 0 V = (V + V )/2 COM A B V A, B V A, B Logical Bit Equivalent Example DAC3482 SLAS748A – MARCH 2011 – REVISED JUNE 2011 www.ti.com Figure 81. Preferred Clock Input Configuration with a Differential ECL/PECL Clock Source LVDS INPUTS The D[15:0]P/N, DATACLKP/N, SYNCP/N, PARITYP/N and FRAMEP/N LVDS pairs have the input configuration shown in Figure 82. Figure 83 shows the typical input levels and common-move voltage used to drive these inputs. Figure 82. D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N and PARITYP/N LVDS Input Configuration Figure 83. LVDS Data Input Levels 68 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DAC3482 |
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