DAC3482 datasheet(48/79 Pages) TI1

48 / 79 page

LPF

S0514-01

R = 1 k

C1 = 100 nF

C2 = 1 nF

DAC3482

SLAS748A

– MARCH 2011 – REVISED JUNE 2011

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When the overall divide ratio is greater than 120, an external loop filter is required to ensure loop stability

The single charge pump current option is selected by setting pll_cp in register config24 to

“01”.

If an external filter is required, the following filter should be connected to the LPF pin (A1):

Figure 56. Recommended External Loop Filter

The PLL will generate an internal OSTR signal and does not require the external LVPECL OSTR signal. The

OSTR signal is buffered from the N-divider output in the PLL block, and the frequency of the signal is the same

as the PFD frequency. Therefore, using PLL with Dual Sync Sources mode requires the PFD frequency to be the

pre-defined OSTR frequency listed in Input FIFO section. This will allow the FIFO to be synced correctly by the

internal OSTR.

MULTI-DEVICE SYNCHRONIZATION

In various applications, such as multi antenna systems where the various transmit channels information is

correlated, it is required that multiple DAC devices are completely synchronized such that their outputs are phase

aligned. The DAC3482 architecture supports this mode of operation.

MULTI-DEVICE SYNCHRONIZATION: PLL BYPASSED WITH DUAL SYNC SOURCES MODE

For single or multi-device synchronization it is important that delay differences in the data are absorbed by the

device so that latency through the device remains the same. Furthermore, to guarantee that the outputs from

each DAC are phase aligned it is necessary that data is read from the FIFO of each device simultaneously. In

the DAC3482 this is accomplished by operating the multiple devices in Dual Sync Sources mode. In this mode

the additional OSTR signal is required by each DAC3482 to be synchronized.

Data into the device is input as LVDS signals from one or multiple baseband ASICs or FPGAs. Data into the

multiple DAC devices can experience different delays due to variations in the digital source output paths or board

level wiring. These different delays can be effectively absorbed by the DAC3482 FIFO so that all outputs are

phase aligned correctly.

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DAC3482 Datasheet(PDF) 48 Page - Texas Instruments