DAC3482 datasheet(11/79 Pages) TI1

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DAC3482

www.ti.com

SLAS748A

– MARCH 2011 – REVISED JUNE 2011

ELECTRICAL CHARACTERISTICS

– DIGITAL SPECIFICATIONS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TIMING OUTPUT STROBE INPUT: DACCLKP/N rising edge LATCHING(3)

Setup time, OSTRP/N

ts(OSTR)

valid to rising edge of

DACCLKP/N

Hold time, OSTRP/N

th(OSTR)

valid after rising edge of

300

DACCLKP/N

TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING (4)

Setup time, SYNCP/N

ts(SYNC_PLL)

valid to rising edge of

200

DACCLKP/N

Hold time, SYNCP/N

th(SYNC_PLL)

valid after rising edge of

300

DACCLKP/N

TIMING SERIAL PORT

Setup time, SDENB to

ts(SDENB)

rising edge of SCLK

Setup time, SDIO valid to

ts(SDIO)

rising edge of SCLK

Hold time, SDIO valid to

th(SDIO)

rising edge of SCLK

µs

t(SCLK)

Period of SCLK

All other registers

100

Data output delay after

td(Data)

falling edge of SCLK

Minimum RESETB pulse

tRESET

width

(3)

OSTR is required in Dual Sync Sources mode. In order to minimize the skew it is recommended to use the same clock distribution

device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the DAC3482 devices in the system.

Swap the polarity of the DACCLK outputs with respect to the OSTR ones to establish proper phase relationship.

(4)

SYNC is required to synchronize the PLL circuit in multiple devices. The SYNC signal must meet the timing relationship with respect to

the reference clock (DACCLKP/N) of the on-chip PLL circuit.

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