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MCD212 Datasheet(PDF) 29 Page - Motorola, Inc |
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MCD212 Datasheet(HTML) 29 Page - Motorola, Inc |
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29 / 87 page  MCD212 4–6 MOTOROLA Table 4–5. Implementing 1M x 4 DRAM Bank 1 Bank 2 DRAM 1 DRAM 2 DRAM 3 DRAM 4 DRAM 5 DRAM 6 DRAM 7 DRAM 8 MD0 – MD3 D0 – D3 D0 – D3 MD4 – MD7 D0 – D3 D0 – D3 MD8 – MD11 D0 – D3 D0 – D3 MD12 – MD15 D0 – D3 D0 – D3 MA0 – MA9 A0 – A9 A0 – A9 A0 – A9 A0 – A9 A0 – A9 A0 – A9 A0 – A9 A0 – A9 LWR W W W W UWR W W W W RAS RAS RAS RAS RAS RAS RAS RAS RAS CAS1 CAS/OE CAS/OE CAS/OE CAS/OE CAS2 CAS/OE CAS/OE CAS/OE CAS/OE Table 4–6. Implementing 256K x 16 DRAM Bank 1 DRAM 1 Bank 2 DRAM 2 MD0 – MD15 D0 – D15 D0 – D15 MA0 – MA8 A0 – A8 A0 – A8 LWR LW LW UWR UW UW RAS RAS RAS CAS1 CAS/OE CAS2 CAS/OE |
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