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MCD212 Datasheet(PDF) 32 Page - Motorola, Inc

Part # MCD212
Description  Video Decoder and System Controller(with JTAG)
PDF  87 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MCD212 Datasheet(HTML) 32 Page - Motorola, Inc

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MCD212
5–3
MOTOROLA
5.2.2
Vertical Resolution
The vertical resolution is dependent on the SM (Scan Mode) bit of the DCR1 register, the FD (Frame
Duration) bit which is also in the DCR1 register, and the ST (Standard) bit which is in the CSR1W
register.
The SM bit controls the scan mode of the VDSC by selecting between the interlace mode and the
non–interlace mode as described in Table 5–3 and shown in Figure 5–3.
Table 5–3. Scan Modes
SM
SCAN Mode Description
0
Non–interlace mode. One image is composed of one field.
1
Interlace mode. One image is composed of two fields.
NON–INTERLACE
MODE
INTERLACE MODE
LINE 1
LINE 2
LINE 3
LINE N
LINE 1
LINE 3
LINE N–1
LINE 5
LINE 2
LINE 4
LINE 6
LINE N
LINE 1
LINE 3
LINE N–1
LINE 5
LINE 2
LINE 4
LINE 6
LINE N
ODD FIELD
+
EVEN FIELD
=
TOTAL IMAGE
IMAGE
••
•
••
•
••
•
••
•
••
•
Figure 5–3. Line Display of Interlace versus Non–interlace Modes
The FD bit and the ST bit only affect the display in the non–interlace mode. They are shown in
Table 5–4.
Table 5–4. Vertical Resolution in the Non–interlace Mode
FD
ST
# of Video Lines
Frame Duration
(ms)
Image
Frequency (Hz)
Display Type
0
0
280
18
50
PAL
1
1
240
15.3
50
PAL
1
x
240
15.3
60
NTSC



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