 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
OR3C80 Datasheet(PDF) 121 Page - Agere Systems |
|
|
|||||||||||||||||||||||||||||
OR3C80 Datasheet(HTML) 121 Page - Agere Systems |
|
|
121 / 210 page  Lucent Technologies Inc. 121 Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 50. Programmable Clock Manager (PCM) Timing Characteristics (Preliminary Information) OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C ≤TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C. * Input frequency tolerance is the allowed input clock frequency change in parts per million. † See Table 29 and Table 30 for acquisition times for individual frequencies. ‡ PLL mode, divider reg = 1111111 (input freq. = output freq.). Note: All timing values for the PCM are preliminary information. Parameter Symbol Speed Unit -4 -5 -6 -7 MinMax MinMax MinMax MinMax Input Clock Frequency: FPCMI OR3Cxx 51335133 — — — — MHz OR3Txxx — — 5 133 5 133 5 133 MHz Output Clock Frequency: FPCMO OR3Cxx 51355135 — — — — MHz OR3Txxx — — 5 100 5 100 5 100 MHz Input Clock Duty Cycle PCMI_DUTY 30.00 70.00 30.00 70.00 30.00 70.00 30.00 70.00 % Output Clock Duty Cycle PCMO_DUTY 3.13 96.90 3.13 96.90 3.13 96.90 3.13 96.90 % Input Frequency Tolerance* FTOL — 26400 — 26400 — 26400 — 26400 ppm PCM Acquisition Time (CLK In to LOCK) PCM_ACQ† 36 100 36 100 36 100 36 100 µs PCM Off Delay (config. Done-L, WE to PCM power off) PCMOFF_DEL — 100.0 — 100.0 — 100.0 — 100.0 ns PCM Delay in DLL Mode (propagation delay) PCMDLL-DEL — 1.95 — 1.82 — 1.63 — 1.50 ns PCM Delay in PLL Mode (propagation delay) PCMPLL_DEL — 0.00 — 0.00 — 0.00 — 0.00 ns PCM Clock In to PCM Clock Out (CLK In to ECLK)‡ PCMBYE_DEL — 0.47 — 0.36 — 0.26 — 0.24 ns PCM Clock In to PCM Clock Out (CLK In to SCLK)‡ PCMBYS_DEL — 0.47 — 0.36 — 0.26 — 0.24 ns Routed Clock-in Delay (routing to PCM phase detect, using DIV0) RTCKD_DEL — 1.30 — 1.10 — 0.90 — TBD ns System Clock-out Delay (PCM oscilla- tor to SCLK output at PCM) PCMSCK_DEL — 2.70 — 2.20 — 1.90 — TBD ns Parameter Symbol fOUT (MHz) PLL Mode DLL Mode Unit Output Jitter OUTJIT 5—20 250 200 ps 21—30 210 170 ps 31—40 180 145 ps 41—50 155 123 ps 51—60 130 105 ps 61—70 110 90 ps 71—80 95 75 ps 81—90 80 65 ps 91—100 70 55 ps |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
