OR3C80 datasheet(124/210 Pages) AGERE

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124

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Timing Characteristics (continued)

Table 53. General-Purpose Clock Timing Characteristics (Internally Generated Clock)

OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C

< TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.

OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C

< TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.

Notes:

This table represents the delay for an internally generated clock from the clock tree input in one of the four middle PICs (using pSW routing) on

any side of the device which is then distributed to the PFU/PIO clock inputs. If the clock tree input used is located at any other PIC, see the

results reported by ORCA Foundry.

This clock delay is for a fully routed clock tree that uses the general clock network. The delay will be reduced if any of the clock branches are not

used. See pin-to-pin timing in Table 56 for clock delays of clocks input on general I/O pins.

Device

(TJ = 85 °C, VDD = min)

Symbol

Speed

Unit

-4

-5

-6

-7

MinMax

OR3T20

CLK_DEL

—

4.22

—

3.46

—

2.84

OR3T30

CLK_DEL

—

4.29

—

3.48

—

2.87

OR3C/T55

CLK_DEL

—

5.34

—

4.41

—

3.53

—

2.93

OR3C/T80

CLK_DEL

—

5.49

—

4.52

—

3.57

—

2.98

OR3T125

CLK_DEL

—

4.80

—

3.71

—

3.13

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