OR3C80 datasheet(127/210 Pages) AGERE

127 / 210 page

Lucent Technologies Inc.

127

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Timing Characteristics (continued)

Table 56. OR3Cxx General System Clock (SCLK) to Output Delay (Pin-to-Pin)

OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C

< TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C; CL = 50 pF.

OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C

< TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C;

CL = 50 pF.

Note:

This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the

PIO CLK input, the clock

→Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not

used. The given timing requires that the input clock pin be located at one of the four center PICs on any side of the device and that a PIO FF be

used. For clock pins located at any other PIO, see the results reported by ORCA Foundry.

5-4846(F)

Figure 78. System Clock to Output Delay

Description

(TJ = 85 °C, VDD = min)

Device

Speed

Unit

-4

-5

-6

-7

Min

Max

Min

Max

Min

Max

Min

Max

Output On Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs)

Clock Input Pin (mid-PIC)

→OUTPUT Pin (Fast)

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

—

14.91

15.71

—

11.35

11.63

12.17

12.80

13.69

—

7.74

7.93

8.28

8.66

9.24

—

6.10

6.27

6.59

6.95

7.49

Clock Input Pin (mid-PIC)

→OUTPUT Pin

(Slewlim)

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

—

17.34

18.14

—

13.34

13.62

14.16

14.79

15.68

—

8.42

8.60

8.95

9.34

9.91

—

6.63

6.80

7.12

7.48

8.02

Clock Input Pin (mid-PIC)

→OUTPUT Pin

(Sinklim)

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

—

18.70

19.51

—

14.69

14.97

15.51

16.14

17.03

—

13.26

13.45

13.80

14.18

14.76

—

11.37

11.54

11.86

12.22

12.76

Additional Delay if Non-mid-PIC Used as Clock

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

—

0.41

0.63

—

0.16

0.20

0.36

0.55

1.11

—

0.18

0.21

0.37

0.57

1.05

—

0.17

0.20

0.35

0.55

1.02

Output Not on Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs)

Additional Delay if Output Not on Same Side as

Input Clock Pin

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

—

0.41

0.63

—

0.16

0.20

0.36

0.55

1.11

—

0.18

0.21

0.37

0.57

1.05

—

0.17

0.20

0.35

0.55

1.02

OUTPUT (50 pF LOAD)

SCLK

PIO FF

OR3C80 Datasheet(PDF) 127 Page - Agere Systems

OR3C80 Datasheet(HTML) 127 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL