OR3C80 datasheet(131/210 Pages) AGERE

131 / 210 page

Lucent Technologies Inc.

131

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Timing Characteristics (continued)

Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin) (continued)

OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C

< TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.

OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C

< TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.

Notes:

The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.

The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer

delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.

5-4847(F).a

Figure 80. Input to Fast Clock Setup/Hold Time

Description

(TJ = 85 °C, VDD = min)

Device

Speed

Unit

-4

-5

-6

-7

MinMax

Input to FCLK Hold Time (middle

ECLK pin, delayed data input)

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

—

0.00

—

0.00

—

0.00

—

0.00

—

Input to FCLK Hold Time (corner

ECLK pin)

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

—

8.43

9.09

—

6.26

6.49

6.98

7.53

8.45

—

5.54

5.72

6.09

6.47

7.10

—

4.88

5.04

5.40

5.79

6.40

—

Input to FCLK Hold Time (corner

ECLK pin, delayed data input)

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

—

0.00

—

0.00

—

0.00

—

0.00

—

ECLK

INPUT

PIO FF

CLKCNTRL

FCLK

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