OR3C80 datasheet(134/210 Pages) AGERE

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134

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Timing Characteristics (continued)

Table 60. General Configuration Mode Timing Characteristics (continued)

OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C

< TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.

OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C

< TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.

Note: TPO is triggered when VDD reaches between 3.0 V to 4.0 V for the OR3Cxx and between 2.7 V and 3.0 V for the OR3Txxx.

Parameter

Symbol

Min

Max

Unit

Slave Parallel Mode

Power-on Reset Delay

CCLK Period:

OR3Cxx

OR3Txxx

Configuration Latency (normal mode):

OR3T20

OR3T30

OR3C55

OR3T55

OR3C80

OR3T80

OR3T125

TPO

TCCLK

TCL

3.90

40.00

15.00

0.36

0.47

1.94

0.72

2.81

1.05

1.64

13.10

—

Partial Reconfiguration (explicit mode):

OR3T20

OR3T30

OR3C55

OR3T55

OR3C80

OR3T80

OR3T125

TPR

0.48

0.54

1.72

0.65

2.04

0.77

0.93

—

µs/frame

INIT

Timing

INIT

High to CCLK Delay:

Slave Parallel

Slave Serial

Master Serial:

(M3 = 1)

(M3 = 0)

Master Parallel:

(M3 = 1)

(M3 = 0)

TINIT_CCLK

1.00

0.50

4.80

1.00

—

3.40

2.00

16.20

3.60

µs

Initialization Latency (PRGM high to INIT high):

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

TIL

0.21

0.24

0.30

0.36

0.45

0.68

0.79

1.00

1.20

1.50

INIT

High to WR, Asynchronous Peripheral

TINIT_WR

2.00

—

µs

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