OR3C80 datasheet(137/210 Pages) AGERE

137 / 210 page

Lucent Technologies Inc.

137

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Timing Characteristics (continued)

Table 62. Master Parallel Configuration Mode Timing Characteristics

OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C

< TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.

OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C

< TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.

Notes:

The RCLK period consists of seven CCLKs for RCLK low and one CCLK for RCLK high.

Serial data is transmitted out on DOUT 1.5 CCLK cycles after the byte is input on D[7:0].

5-6764(F)

Figure 84. Master Parallel Configuration Mode Timing Diagram

Parameter

Symbol

Min

Max

Unit

RCLK to Address Valid

TAV

—

60.00

D[7:0] Setup Time to RCLK HighTS

60.00

—

D[7:0] Hold Time to RCLK HighTH

0.00

—

RCLK Low Time (M3 = 0)

TCL

7.00

CCLK cycles

RCLK High Time (M3 = 0)

TCH

1.00

CCLK cycles

RCLK Low Time (M3 = 1)

TCL

7.00

CCLK cycles

RCLK High Time (M3 = 1)

TCH

1.00

CCLK cycles

CCLK to DOUT

—5.00

A[17:0]

RCLK

D[7:0]

TCL

TCH

TAV

CCLK

DOUT

BYTE N

BYTE N + 1

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